About data alignment
in [Visual C]
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From: Scott McPhillips [MVP] on 28 Apr 2008 09:31 "K�rsat" <xx(a)yy.com> wrote in message news:e24BBKSqIHA.1772(a)TK2MSFTNGP03.phx.gbl... > Ok, if I understand correctly; a 32-bit CPU can generate any 32-bit > address using it's address lines but it can not use every address' to read > data from RAM. Excellent but I still can't grasp the reason. CPU can put > any address into the address bus and memory controller should read bytes > starting from that address and put them into the data bus. Some > limitations about CPU or memory controller should cause that alignment > issues. The low two address lines are not used by the memory if the data bus is 32 bits. All memory reads bring 32 bits into the CPU. If the desired byte/word is not properly aligned then it would come in to the wrong bytes of the destination CPU register. Kind of like a train coming in to the station but on the wrong track. Some cases might even require two 32-bit reads to get the two halves of a word. In such cases some CPUs can shuffle the bytes to get them properly aligned in the destination register. But some CPUs can't. -- Scott McPhillips [VC++ MVP]
From: Ben Voigt [C++ MVP] on 29 Apr 2008 18:22 Scott McPhillips [MVP] wrote: > "K�rsat" <xx(a)yy.com> wrote in message > news:e24BBKSqIHA.1772(a)TK2MSFTNGP03.phx.gbl... >> Ok, if I understand correctly; a 32-bit CPU can generate any 32-bit >> address using it's address lines but it can not use every address' >> to read data from RAM. Excellent but I still can't grasp the reason. >> CPU can put any address into the address bus and memory controller >> should read bytes starting from that address and put them into the >> data bus. Some limitations about CPU or memory controller should >> cause that alignment issues. > > The low two address lines are not used by the memory if the data bus > is 32 bits. All memory reads bring 32 bits into the CPU. If the Which is to say, the different bits are stored in different memory chips, each attached to a separate wire of the data bus. There's no way to get byte 3's data to appear on D[7-0] because it's stored in the memory chips connected to D[31-24]. > desired byte/word is not properly aligned then it would come in to > the wrong bytes of the destination CPU register. Kind of like a > train coming in to the station but on the wrong track. Some cases > might even require two 32-bit reads to get the two halves of a word. In > such cases some CPUs can shuffle the bytes to get them properly > aligned in the destination register. But some CPUs can't.
From: K�r�at on 30 Apr 2008 03:38
Thanks Ben, this is what I want to hear. Can you recommend any resource about architectural issues like this? "Ben Voigt [C++ MVP]" <rbv(a)nospam.nospam> wrote in message news:u9EV$bkqIHA.524(a)TK2MSFTNGP05.phx.gbl... > Scott McPhillips [MVP] wrote: >> "K�rsat" <xx(a)yy.com> wrote in message >> news:e24BBKSqIHA.1772(a)TK2MSFTNGP03.phx.gbl... >>> Ok, if I understand correctly; a 32-bit CPU can generate any 32-bit >>> address using it's address lines but it can not use every address' >>> to read data from RAM. Excellent but I still can't grasp the reason. >>> CPU can put any address into the address bus and memory controller >>> should read bytes starting from that address and put them into the >>> data bus. Some limitations about CPU or memory controller should >>> cause that alignment issues. >> >> The low two address lines are not used by the memory if the data bus >> is 32 bits. All memory reads bring 32 bits into the CPU. If the > > Which is to say, the different bits are stored in different memory chips, > each attached to a separate wire of the data bus. There's no way to get > byte 3's data to appear on D[7-0] because it's stored in the memory chips > connected to D[31-24]. > >> desired byte/word is not properly aligned then it would come in to >> the wrong bytes of the destination CPU register. Kind of like a >> train coming in to the station but on the wrong track. Some cases >> might even require two 32-bit reads to get the two halves of a word. In >> such cases some CPUs can shuffle the bytes to get them properly >> aligned in the destination register. But some CPUs can't. > > |