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From: M. Hamed on 11 Aug 2010 19:02
Hello there,

I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.

None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.

We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.

Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.

Help is appreciated! Thanks.
From: linnix on 11 Aug 2010 19:17
On Aug 11, 4:02 pm, "M. Hamed" <mhels...(a)hotmail.com> wrote:
> Hello there,
>
> I'm part of a team that has been assigned the task of designing a
> system consisting of a backplane and a number of daughter board.

Q#1: How many daughters?

Q#2: Are you sure they can't be serially communicated.



From: markp on 11 Aug 2010 20:03

"M. Hamed" <mhelshou(a)hotmail.com> wrote in message
news:40703d15-7a81-4a50-939e-accabe44b6be(a)k1g2000prl.googlegroups.com...
> Hello there,
>
> I'm part of a team that has been assigned the task of designing a
> system consisting of a backplane and a number of daughter board. Each
> daughter board will have a large number of chips. The main board will
> need to communicate with one chip at a time but the communication
> lines will go to every single chip and it's up to a controller
> (possibly on the daughter board) to enable each chip individually.
>
> None of us has enough experience with stacks of boards or backplanes.
> We are worried that connecting one signal line to that many boards and
> chips will introduce too many signal integrity problems and
> capacitance that will make it impossible.
>
> We are not sure whether the best topology would be a backplane and a
> bunch of daughter boards connected via edge connectors or a stack of
> boards with each board plugging into the board below it and the bottom
> daughter board connecting to the backplane/motherboard. We think that
> the latter approach would be worse especially for the boards higher up
> in the stack of boards.
>
> Can someone provide some advice over how to go about designing this
> and what could be possible solutions? Are there any established design
> practices? Are there any technical terms we should be looking up or
> certain resources we should be consulting? As I mentioned we don't
> have enough experience with this kind of problem. Most of what we've
> done was single board systems.
>
> Help is appreciated! Thanks.

Is it a parallel bus or serial? What bandwidth do you need? Would RS485 do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for the
backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each line
and at each end of the backplane (or you can use active termination). VME
also defines the driver characteristics, and you can buy chips specifically
for VME. There should only be one load on each signal, and the drivers
mounted close to the connectors to minimise stub lengths (which are 3 row
DIN41612 type for standard VME16 and VME32).

Mark.


From: markp on 11 Aug 2010 20:19

"markp" <map.nospam(a)f2s.com> wrote in message
news:8cgs1mF7utU1(a)mid.individual.net...
>
> "M. Hamed" <mhelshou(a)hotmail.com> wrote in message
> news:40703d15-7a81-4a50-939e-accabe44b6be(a)k1g2000prl.googlegroups.com...
>> Hello there,
>>
>> I'm part of a team that has been assigned the task of designing a
>> system consisting of a backplane and a number of daughter board. Each
>> daughter board will have a large number of chips. The main board will
>> need to communicate with one chip at a time but the communication
>> lines will go to every single chip and it's up to a controller
>> (possibly on the daughter board) to enable each chip individually.
>>
>> None of us has enough experience with stacks of boards or backplanes.
>> We are worried that connecting one signal line to that many boards and
>> chips will introduce too many signal integrity problems and
>> capacitance that will make it impossible.
>>
>> We are not sure whether the best topology would be a backplane and a
>> bunch of daughter boards connected via edge connectors or a stack of
>> boards with each board plugging into the board below it and the bottom
>> daughter board connecting to the backplane/motherboard. We think that
>> the latter approach would be worse especially for the boards higher up
>> in the stack of boards.
>>
>> Can someone provide some advice over how to go about designing this
>> and what could be possible solutions? Are there any established design
>> practices? Are there any technical terms we should be looking up or
>> certain resources we should be consulting? As I mentioned we don't
>> have enough experience with this kind of problem. Most of what we've
>> done was single board systems.
>>
>> Help is appreciated! Thanks.
>
> Is it a parallel bus or serial? What bandwidth do you need? Would RS485 do
> the job?
>
> Stacking is going to cause a lot of signal integrity issues, I'd go for
> the backplane (like in a 3U or 6U rack)
>
> If you are thinking parallel bus, the VMEbus backplane is a good example.
> Basically you need to control the impedance of the backplane PCB. VME
> backplanes are quite thick, and need termination resistor pairs on each
> line and at each end of the backplane (or you can use active termination).
> VME also defines the driver characteristics, and you can buy chips
> specifically for VME. There should only be one load on each signal, and
> the drivers mounted close to the connectors to minimise stub lengths
> (which are 3 row DIN41612 type for standard VME16 and VME32).
>
> Mark.
>

BTW high speed parallel backplane design is a tricky subject and somewhat of
a black art, you really need to know what you're doing to avoid problems.
Also you'll need to test it thoroughly with some good test gear. You might
find it quicker and easier to buy an off-the-shelf VME rack or backplane
(such as those from BICC-VERO,) use the DIN41612 connectors and the VME
driver chips on your cards, even if you end up implementing your own bus
protocol instead of VME. At least that way you'll avoid some signal
integrity issues.

Mark.


From: M. Hamed on 11 Aug 2010 20:30
On Aug 11, 5:03 pm, "markp" <map.nos...(a)f2s.com> wrote:
> Is it a parallel bus or serial? What bandwidth do you need? Would RS485 do
> the job?
>
> Stacking is going to cause a lot of signal integrity issues, I'd go for the
> backplane (like in a 3U or 6U rack)
>
> If you are thinking parallel bus, the VMEbus backplane is a good example.
> Basically you need to control the impedance of the backplane PCB. VME
> backplanes are quite thick, and need termination resistor pairs on each line
> and at each end of the backplane (or you can use active termination). VME
> also defines the driver characteristics, and you can buy chips specifically
> for VME. There should only be one load on each signal, and the drivers
> mounted close to the connectors to minimise stub lengths (which are 3 row
> DIN41612 type for standard VME16 and VME32).
>
> Mark.

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

The design I was thinking of is probably a backplane that has an on-
board controller. The controller would receive commands from a PC
through USB or serial. Each daughter board would be enabled one at a
time using relays. Perhaps using MOSFETs for turning on power and
relays for routing clock and data. Once a daughter board is enabled,
another on-daughter-board controller (instructed by the main-board
controller) would route the signals to each chip perhaps using analog
switches or another set of relays. I don't know if this is too much
from a signal integrity standpoint.

The serial bandwidth is somewhere from 5 MHz to 20 MHz, i.e. each
serial clock would take from 50 ns to 200ns. The faster the better but
we could make it slower if signal integrity problems are unsolvable at
the high speed.

Does that sound reasonable? I'm also not sure how we would go about
characterizing capacitances, impedances, and such.
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