Call VHDL module from Verilog
in [FPGA]
|
From: egadget1 on 6 May 2008 15:38 Hi, I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I don't want to recode it in verilog. Thanks Rob
From: egadget1 on 6 May 2008 16:52 On May 6, 3:38 pm, egadget1 <rnu...(a)gmail.com> wrote: > Hi, > > I have a basic question. Is is possible in the xilinx ISE enviroment > to make a verilog wrapper of some VHDL code. I don't want to recode > it in verilog. > > Thanks > Rob Never mine I figured it out. Rob
From: Mike Treseler on 6 May 2008 17:01 egadget1 wrote: >> I have a basic question. Is is possible in the xilinx ISE enviroment >> to make a verilog wrapper of some VHDL code. I don't want to recode >> it in verilog. >> >> Thanks >> Rob > > Never mind I figured it out. The rule is, you have to tell us what you did ;)
|
Pages: 1 Prev: Aldec Active-HDL 7.3 sp1 [stimulators] Next: Forking in One-Hot FSMs |