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From: songrise on 22 Apr 2008 18:58
Hi all,

I don't understand is there any the relationship between the value of
period constraints and my input clock?

For my system, Board input clock is 50MHz, system works at 500MHz.
When there is no timing constraints: Chipscope result is not right:
some signals should be all zero while they show certain pulses, which
are shorter than normal. Although the chipscope output becomes right
when I add 60 ns period timing constraints, but i don't know why this
happens, what does the 60ns means? is it too long a time for the
system? if i add 20ns, it won't pass the implementation. By the way,
there are 160X8bits registers being used in the system. and the device
is Virtex-5, XC5VLX110T,

1, When there is no timing constraints:( Chipscope result is not
right: some signals should be all zero while they show certain pulses,
which are shorter than normal.)
Timing errors: 0 Score: 0
Constraints cover 2171 paths, 0 nets, and 695 connections
Design statistics:
Minimum period: 4.138ns (Maximum frequency: 241.663MHz)
Maximum path delay from/to any node: 4.138ns

2, When i add 20 ns period timing constraints, error occurs as: Pack:
1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the
constraint. A physical timing constraint summary will appear in the
map report. This summary will show a MINIMUM net delay for the
paths. For more information about the Timing Analyzer, consult the
Xilinx Timing Analyzer Reference manual. For more information on
TRCE, consult the Xilinx Development System Reference Guide "TRACE"
chapter.


3, When i add 60 ns period timing constraits, there will be no problem
from Chipscope,

Timing errors: 0 Score: 0
Constraints cover 38571 paths, 0 nets, and 4430 connections
Design statistics:
Minimum period: 6.175ns (Maximum frequency: 161.943MHz)
Maximum path delay from/to any node: 6.175ns
Minimum input required time before clock: 3.585ns
Minimum output required time after clock: 4.935ns

Thank you all.
From: Symon on 23 Apr 2008 10:28
http://toolbox.xilinx.com/docsan/xilinx92/books/docs/cgd/cgd.pdf


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