Computer Architecture
in [Hardware]
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Extended Deadline - ALTA 2008 CFP Paper submission deadline: EXTENDED: April 21, 2008 Architectures and Languages for Throughput Applications (ALTA 2008) Held in conjunction with the 2008 International Symposium on Computer Architecture (ISCA-35) Sunday June 22nd, Beijing, China http://www.sei.buaa.edu.cn/alta08/ Submitted papers will... 14 Apr 2008 14:36
Hinted conditional branch ? Out of curiosity : Are there or have there ever been processors with different instructions for conditional branches likely to be taken and conditional branches UNlikely to be taken ? If so, did/does that help ? -- Andr� Majorel <URL:http://www.teaser.fr/~amajorel/> (Counterfeit: ijif(a)charon.com zonos(a)whi... 17 Apr 2008 16:33
Method for Computer Technology Monopolization CompanyA develops computer software. ( ei. rips off the best ideas from whoever, are remarketed using altered terminology which is of course highly publicized, ( Does "PC" mean "Private Computing" or "Personal Computerization?")) Company B develops computer hardware. ( ditto ) Company C markets new software a... 13 Apr 2008 11:55
laptop life & battery capacity Jonathan Thornburg [remove -animal to reply] wrote: Morten Reistad wrote: | There is nothing barring us from making a laptop you can work on for | a day or so with normal battery cappactities. 6Ah @ 14V is about the | limit, or 84Wh. That means we would need to limit power for the system | to an average ... 13 Apr 2008 06:09
laptop life & battery capacity (was: Re: performance of hardware dynamic scheduling) Morten Reistad wrote: | There is nothing barring us from making a laptop you can work on for | a day or so with normal battery cappactities. 6Ah @ 14V is about the | limit, or 84Wh. That means we would need to limit power for the system | to an average of 8W. Bill Todd <billtodd(a)metrocast.net> wrote: I have n... 13 Apr 2008 05:22
MIPS UDI hello, all. in my association with MIPS architecture as a programmer one thing i could never experiment with is the MIPS UDI or the user defined instructions co-processor. wondering if anybody has evaluated or deployed it. how close does this trick(?) goes to the re-configurable architectures? also what abou... 12 Apr 2008 19:05
Prodigious website troll (was: Intel, Nvidia...) AirRaid wrote: [SPAM]By Michael Hatamoto, BetaNews[SPAM] http://groups.google.com/groups/search?q=betanews.com&scoring=d&filter=0&num=100 ... 11 Apr 2008 19:52
Cache Simulator Required Does anyone know some web based or open source Cache Simulator that takes input of user code and based on that code; simulates the cache(just like benchmark). regards ... 12 Apr 2008 06:09
Core - how many instructions per cycle? "Intel's literature states that Core can, for example, execute a 128-bit packed multiply, 128-bit packed add, 128-bit packed load, 128-bit packed store, and a macro-fused cmpjcc (a compare + a jump on condition code) all in the same cycle. That's essentially six instructions in one cycle�quite a boost from any pr... 12 Apr 2008 12:42
Difference between On-Chip RAM and On-Chip Cache Hi there Can anyone tell me about the difference between on-chip RAM and on- Chip cache. Is there any latency difference? If yes then why? Regards ... 6 May 2008 22:20 |