Computer Architecture
in [Hardware]
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CFP: Special Issue of ACM SIGOPS OSR The Interaction among the OS, the Compiler, and Multicore Processors Special Issue of ACM Operating System Review http://www.cs.virginia.edu/kim/publicity/osr09/ The interaction among operating systems, compilers, and multicore processors is becoming more tightly boun... 26 Aug 2008 12:59
Von Neumann and revisionists [Re: Future architectures [was Re: Intel details future Larrabee ...]] In article <e6146e54-9c0b-4eab-b5fa-fd6c81ee1b05(a)k7g2000hsd.googlegroups.com>, already5chosen(a)yahoo.com writes: |> > |> > http://portal.acm.org/citation.cfm?id=359579 |> |> Sorry, ACM portal refuses to show me what you mean. It refuses to show me, now. Try the following for the full article: http... 25 Aug 2008 09:19
Von Neumann and revisionists [Re: Future architectures [was Re: Intel details future Larrabee ...]] In article <411fa0ee-729c-4c18-81b0-abaebdeef239(a)l42g2000hsc.googlegroups.com>, already5chosen(a)yahoo.com writes: |> > |> Conclusion: the people that use the term "Von Neumann architecture" as |> a common replacement for "architecture based on interpreting of serial |> or near-serial instruction streams fetched f... 25 Aug 2008 09:19
Von Neumann and revisionists [Re: Future architectures [was Re: Intel details future Larrabee ...]] On Aug 25, 2:03 pm, n...(a)cus.cam.ac.uk (Nick Maclaren) wrote: In article <08a5536f-f6aa-495a-b0c2-09685471a...(a)l64g2000hse.googlegroups.com>,already5cho...(a)yahoo.com writes: To some extent, even you are a revisionist, because the traditional terminology "Von Neumann architecture" includes the Harvard varian... 1 Sep 2008 01:53
triple word accumulator Hello, on small 32bit architectures, like the original m68000 and the original sparc, would an accumulator of three times the integer register size = 96bit have been helpful? Similar, can it be helpful on todays small 32bit architectures in embedded and multicore designs? A somewhat vague description of wh... 26 Aug 2008 16:05
Future architectures [was Re: Intel details future Larrabee...] On Sat, 23 Aug 2008 19:24:15 +0200, Terje Mathisen wrote: I.e. FFT/DCT runs better with a precalculated array of pairs of indices to be swapped, since that avoids all the need for branch prediction within the inner loop: From: ai = bitrev(i); if (ai < i) swap(data[i], data[ai]); ... 27 Aug 2008 22:49
Some confusion about virtual cache Hi, I am trying to understand how virtually indexed, physically tagged cache works. And I have some confusion. Let just assume that page offset is 12 bit and virtual and physical addresses are 32 bit. What will be the tag if the lower, say, 16 bits of a virtual address are used to index the cache? Will it be 20 bi... 14 Sep 2008 09:38
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Future architectures nmm1(a)cus.cam.ac.uk (Nick Maclaren) writes: I knew then when Intel 286 so-called virtual memory looked like, and I don't call it virtual memory. Nor, interestingly, did most of the people in IBM I talked to - they took a HELL of a long time to learn about virtual memory, but did eventually learn. Other ... 27 Aug 2008 11:31 |