From: Bob on
Hi Group

I have a non quadrature signal at 3 MHz. I need to convert it to
quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing
rate at the next stage. What do you experts think would be the best
method in terms of resources (for an fpga) or is there much
difference?

1 Hilbert Transformer
2 Multiply by a 1.5 Mhz sine and cosine and then filter to get rid of
the 4.5 Mhz sum signal.

Alternatively, are there any smart tricks that could do this more
efficiently?

Many Thanks
Bob
From: Tim Wescott on
Bob wrote:
> Hi Group
>
> I have a non quadrature signal at 3 MHz. I need to convert it to
> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing
> rate at the next stage. What do you experts think would be the best
> method in terms of resources (for an fpga) or is there much
> difference?
>
> 1 Hilbert Transformer
> 2 Multiply by a 1.5 Mhz sine and cosine and then filter to get rid of
> the 4.5 Mhz sum signal.
>
> Alternatively, are there any smart tricks that could do this more
> efficiently?

Either will work, and it's probably a toss up whether 1 or 2 is best in
terms of circuit area and speed requirements (both have been done in
analog circuits).

But this is a little block in a bigger system, and you're doing
something that -- on the face of it -- sounds a bit odd. What are you
really trying to do? Normally you want I and Q signals so you can do
your processing at baseband. Why don't you demodulate it straight down
to DC by multiplying it by 3MHz sine and cosine waves, and filtering as
appropriate?

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
From: Jerry Avins on
Bob wrote:
> Hi Group
>
> I have a non quadrature signal at 3 MHz. I need to convert it to
> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing
> rate at the next stage. What do you experts think would be the best
> method in terms of resources (for an fpga) or is there much
> difference?
>
> 1 Hilbert Transformer
> 2 Multiply by a 1.5 Mhz sine and cosine and then filter to get rid of
> the 4.5 Mhz sum signal.
>
> Alternatively, are there any smart tricks that could do this more
> efficiently?

You will have to process the same number of samples either way. 1.5M I
plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz
bandwidth, you need 3 M samples/sec. They can be all regular samples,
half I and half Q, half I and half dI/dt, or any other set.

Jerry
--
Discovery consists of seeing what everybody has seen, and thinking what
nobody has thought. .. Albert Szent-Gyorgi
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From: glen herrmannsfeldt on
Jerry Avins <jya(a)ieee.org> wrote:

>> I have a non quadrature signal at 3 MHz. I need to convert it to
>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing
>> rate at the next stage. What do you experts think would be the best
>> method in terms of resources (for an fpga) or is there much
>> difference?
(snip)

> You will have to process the same number of samples either way. 1.5M I
> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz
> bandwidth, you need 3 M samples/sec. They can be all regular samples,
> half I and half Q, half I and half dI/dt, or any other set.

There might be some cases where quadrature sampling is better,
though I am not convinced that there are many.

3MHz isn't fast, so speed probably isn't the reason here.

In the case where speed is, you can put two ADCs outside the
FPGA and separately clock the two. (Ignoring problems due to
non-linearity in the ADCs.)

Now, is it better to do the IQ conversion in the analog domain
and then send it into the FPGA (More analog circuitry, less
FPGA resources) or just sample and ADC at 3MHz, and do the
IQ conversion in digital logic?

It seems to me that to do it right, you need carefully matched
analog filters, where it is easy to do in the digital domain
without worry about matching of filters.

-- glen
From: Tim Wescott on
glen herrmannsfeldt wrote:
> Jerry Avins <jya(a)ieee.org> wrote:
>
>>> I have a non quadrature signal at 3 MHz. I need to convert it to
>>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing
>>> rate at the next stage. What do you experts think would be the best
>>> method in terms of resources (for an fpga) or is there much
>>> difference?
> (snip)
>
>> You will have to process the same number of samples either way. 1.5M I
>> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz
>> bandwidth, you need 3 M samples/sec. They can be all regular samples,
>> half I and half Q, half I and half dI/dt, or any other set.
>
> There might be some cases where quadrature sampling is better,
> though I am not convinced that there are many.
>
> 3MHz isn't fast, so speed probably isn't the reason here.
>
> In the case where speed is, you can put two ADCs outside the
> FPGA and separately clock the two. (Ignoring problems due to
> non-linearity in the ADCs.)
>
> Now, is it better to do the IQ conversion in the analog domain
> and then send it into the FPGA (More analog circuitry, less
> FPGA resources) or just sample and ADC at 3MHz, and do the
> IQ conversion in digital logic?
>
> It seems to me that to do it right, you need carefully matched
> analog filters, where it is easy to do in the digital domain
> without worry about matching of filters.
>
> -- glen

Potayto, potahto.

Mathematically it's the same to do it in analog or digital. Practically
you have all sorts of channel matching issues if you do it in analog, so
if you can get away with it, you'd rather just sample fast and
downconvert digitally.

3MHz is very slow these days.

I'd go as far as to say that if you _did_ have a carrier that was too
fast for all-digital conversion, and unless bandwidth considerations
ruled it out, you'd be better off to do a traditional superhet stage to
a lower IF, filter, and downconvert to baseband from there.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com