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From: Rick Lyons on 4 May 2008 14:00
On Sun, 4 May 2008 02:58:36 -0700 (PDT), Rudheesh Raghav
<rudheeshrk(a)gmail.com> wrote:

>On May 4, 7:31�am, Rick Lyons <R.Lyons@_BOGUS_ieee.org> wrote:
>> On Mon, 28 Apr 2008 15:08:06 -0700 (PDT), Rudheesh Raghav
>>
>>
>>
>> <rudhees...(a)gmail.com> wrote:
>> >Hi all,
>>
>> > � � � � I would like to have some help from you in this topic.
>>
>> >I have converted a 12.1MHz analog IF signal to baseband using an
>> >105MSPS ADC and a Virtex-4 FPGA. But I'm getting a DC offset of about
>> >20% of peak to peak value.
>>
>> >The BW of the Signal is 200 KHz.
>>
>> >What is the best method of DC offset Cancellation??
>>
>> >Can I do averaging over a period of time and subtract the average or
>> >can I use a High Pass Filter??
>>
>> >If averaging is the correct way, How long I should average??
>>
>> > � � � � � � � � � � � � � � � � thanks in advance
>>
>> >Rudheesh
>>
>> Hello Rudheesh,
>> � �You might have a look at the "DSP Tips & Tricks"
>> column in the March 2008 issue of the IEEE Signal
>> Proc. magazine. �That column is an article titled
>> "DC Blocker Algorithms", written by our own Randy Yates,
>> some other guy. �Perhaps it'll be of some use to you.
>>
>> Goos Luck,
>> [-Rick-]
>
>Hi Rick,
>
> Thank you for the information.
>
>What may be the possible sources of DC Offset in a Digital Down
>Converter except from DC offset in the source?

Hi,
Humm, it may be possible that, depending on the
signal being down-converted, that (1) amplitude
mismatch and/or (2) non-90 degree phasing of the oscillators
in "quadrature oscillator" may cause a DC bias error
in the down-converted signal.
I'm blurting things out here of the top of my head,
so I wouldn't trust me if I were you.

I'm tryin' to think of phrases you can 'Google on'.
Maybe:

phase mismatch
phase offset
quadrature oscillators
amplitude mismatch

It seems to me that "down-coverter" and
"up-converter" tutorials on the Internet should
discuss the effects of "imperfect oscillators".

Good Luck,
[-Rick-]

From: Rick Lyons on 4 May 2008 13:50
On Sat, 3 May 2008 20:36:23 -0700 (PDT), rickman <gnuarm(a)gmail.com>
wrote:

>On May 3, 10:31 pm, Rick Lyons <R.Lyons@_BOGUS_ieee.org> wrote:
>> On Mon, 28 Apr 2008 15:08:06 -0700 (PDT), Rudheesh Raghav
>>
>>
>>
>> <rudhees...(a)gmail.com> wrote:
>> >Hi all,
>>
>> > I would like to have some help from you in this topic.
>>
>> >I have converted a 12.1MHz analog IF signal to baseband using an
>> >105MSPS ADC and a Virtex-4 FPGA. But I'm getting a DC offset of about
>> >20% of peak to peak value.
>>
>> >The BW of the Signal is 200 KHz.
>>
>> >What is the best method of DC offset Cancellation??
>>
>> >Can I do averaging over a period of time and subtract the average or
>> >can I use a High Pass Filter??
>>
>> >If averaging is the correct way, How long I should average??
>>
>> > thanks in advance
>>
>> >Rudheesh
>>
>> Hello Rudheesh,
>> You might have a look at the "DSP Tips & Tricks"
>> column in the March 2008 issue of the IEEE Signal
>> Proc. magazine. That column is an article titled
>> "DC Blocker Algorithms", written by our own Randy Yates,
>> some other guy. Perhaps it'll be of some use to you.
>>
>> Goos Luck,
>> [-Rick-]
>
>Can you recommend a way to get that article without spending $13? I
>guess even though I am an IEEE member, I still have to pay for
>articles from magazines I don't subscribe to.

Hi,
Yes, there is a way. It's legal for the
authors to distrubute copies of their
articles. Please send me a private E-mail
& I can solve you problem.

Regards,
[-Rick-]

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