DCM spartan 3 variable frequency divider
in [FPGA]
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From: Monica on 4 Jan 2006 09:07 Hello all, I am monica from germany.I am using xilinx spartan 3 FPGA.I have a peculiar problem with DCM in spartan 3 FPGA. The input frequency to the FPGA is from another system which gives a frequency arround 40 MHz and the FPGA is supposed to generate 1/8 th of the input frequency,I have implemented it by using DCM.dcmLocked is asserted(dcm locked) and it works fine. On certain conditions the input frequency changes from 40 MHz to 60MHz,now dcmLocked is still asserted(shows that dcm locked) but the output divided clock's duty cycle is not 50% it is varying spuriously which is really annoying. i think DCM still thinks that it is having 40MHz input signal and tries to lock to it,but it is giving dcmLocked as '1' which is wrong.Either it should give dcmLocked as '0' or give the correct clock output,but it is giving wrong clock output as well as wrong dcmLocked signal. Can anybody give me an idea how to solve this frequency division problem? I will be obliged if anyone can give me a hint/pointers to solve this problem. Thank you very much Monica Dsouza, Germany
From: John Adair on 4 Jan 2006 09:16 Monica The "locked" signal is notoriously unreliable and basically shouldn't be used. The status lines are better. Generally if your frequency changes like that I would recommend applying a reset to the DCM if possible. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 Development Board. http://www.enterpoint.co.uk "Monica" <monica_dsz(a)yahoo.com> wrote in message news:1136383667.647681.243150(a)o13g2000cwo.googlegroups.com... > Hello all, > > I am monica from germany.I am using xilinx spartan 3 FPGA.I have a > peculiar problem with DCM in spartan 3 FPGA. > > The input frequency to the FPGA is from another system which gives a > frequency arround 40 MHz and the FPGA is supposed to generate 1/8 th of > the input frequency,I have implemented it by using DCM.dcmLocked is > asserted(dcm locked) and it works fine. > > On certain conditions the input frequency changes from 40 MHz to > 60MHz,now dcmLocked is still asserted(shows that dcm locked) but the > output divided clock's duty cycle is not 50% it is varying spuriously > which is really annoying. > > i think DCM still thinks that it is having 40MHz input signal and tries > to lock to it,but it is giving dcmLocked as '1' which is wrong.Either > it should give dcmLocked as '0' or give the correct clock output,but it > is giving wrong clock output as well as wrong dcmLocked signal. > > Can anybody give me an idea how to solve this frequency division > problem? > > I will be obliged if anyone can give me a hint/pointers to solve this > problem. > > Thank you very much > Monica Dsouza, > Germany >
From: Monica on 4 Jan 2006 10:03 Hallo, Thank you very much for the suggestion. If I understand the datasheet of the DCM correctly,status bits indicate the following things. status[0] indicate if phase shifter has reached its maximum value status[1] indicate if CLKIN is present or not status[2] indicate CLKFX and CLKFX180 are present or not and remaining status bits are reserved(invalid). How can we determine whether DCM has locked or not using these status lines?Did I interpret the data sheet incorrectly? yes I will reset the DCM if it can show that it is not locked.The problem is it is showing that it has locked but giving incorrect clock.if it can give an indication that it cannot lock or lock is lost,then I can reset the DCM. Unfortunately system which changes the frequency cannot reset or give an indication to the FPGA.if we have to do it then we must redesign our hardware to give an addtional line from that system to the FPGA.We will do it only if nothing else can be done to solve the problem(because it costs heavily). Kindly let me know how can i deal with this problem. Thank you very much, Monica
From: John Adair on 4 Jan 2006 10:33 Monica The status lines may not be enough. Depending on what happens when you clock changes but you may get the "not present" showing long enough that you can register the event. Other ways to detect clocks running fast or slow but usually you need some kind of reference clock to compare or run logic from. With the large step frequency you have it would be easy to detect. Either way you will need more than the DCM alone to get an indicator. I don't think Xilinx every envisaged coping with a dynamic clock input as you describe. DCMs tend to like nice stable clocks. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Monica" <monica_dsz(a)yahoo.com> wrote in message news:1136387011.980099.285940(a)f14g2000cwb.googlegroups.com... > Hallo, > > Thank you very much for the suggestion. > > If I understand the datasheet of the DCM correctly,status bits indicate > the following things. > > status[0] indicate if phase shifter has reached its maximum value > status[1] indicate if CLKIN is present or not > status[2] indicate CLKFX and CLKFX180 are present or not > and remaining status bits are reserved(invalid). > > How can we determine whether DCM has locked or not using these status > lines?Did I interpret the data sheet incorrectly? > > yes I will reset the DCM if it can show that it is not locked.The > problem is it is showing that it has locked but giving incorrect > clock.if it can give an indication that it cannot lock or lock is > lost,then I can reset the DCM. > > Unfortunately system which changes the frequency cannot reset or give > an indication to the FPGA.if we have to do it then we must redesign our > hardware to give an addtional line from that system to the FPGA.We will > do it only if nothing else can be done to solve the problem(because it > costs heavily). > > Kindly let me know how can i deal with this problem. > > Thank you very much, > Monica >
From: Monica on 4 Jan 2006 11:11
Dear John Adair, Thank you very much for the reply.I need an addtional lines to the FPGA to indicate this frequency change.Time to fight with PCB engineer to provide one additional line. Thanks a lot, Monica |