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From: Del Cecchi on 11 Apr 2008 10:25

"PhD Student" <yasirqadri(a)yahoo.com> wrote in message
news:505d4854-2021-476b-bd7f-fdbb7d37d71b(a)2g2000hsn.googlegroups.com...
On Apr 11, 7:39 am, joachim.stromberg...(a)gmail.com wrote:
> On 11 Apr, 03:50, "Stephen Sprunk" <step...(a)sprunk.org> wrote:
>
> > "PhD Student" <yasirqa...(a)yahoo.com> wrote in message
>
> >news:a677a8b2-b712-480c-b19f-6783a94d1763(a)b9g2000prh.googlegroups.com...
>
> > > Can anyone tell me about the difference between on-chip RAM and on-
> > > Chip cache. Is there any latency difference? If yes then why?
>
> > Cache is usually SRAM when speaking of processors. On-chip "RAM"
> > might
> > refer to SRAM or DRAM, depending on the context, but today is most
> > likely
> > also SRAM.
>
> Another big difference between SRAM based on-chip RAM and SRAM based
> on-chip cache is associativity, update/replacement policy support etc
> all of which makes the cache much more complex.
>
> /JoachimS

Yes I know; but please refer to Renesas microcontrollers having on-
chip RAM and Cache. What I want to know is; if the RAM and Cache both
are implemented using SRAM; then why in some architectures they co-
exist. Does the size of memory also effect the latency?
Regards
-----------------------------
Do you understand what cache is and how it is made? Perhaps if you
studied up on that you might comprehend what folks are saying.


From: JoachimS on 6 May 2008 15:28
On Apr 11, 11:12 am, PhD Student <yasirqa...(a)yahoo.com> wrote:
> On Apr 11, 7:39 am, joachim.stromberg...(a)gmail.com wrote:
>
>
>
> > On 11 Apr, 03:50, "Stephen Sprunk" <step...(a)sprunk.org> wrote:
>
> > > "PhD Student" <yasirqa...(a)yahoo.com> wrote in message
>
> > >news:a677a8b2-b712-480c-b19f-6783a94d1763(a)b9g2000prh.googlegroups.com...
>
> > > > Can anyone tell me about the difference between on-chip RAM and on-
> > > > Chip cache. Is there any latency difference? If yes then why?
>
> > > Cache is usually SRAM when speaking of processors. On-chip "RAM" might
> > > refer to SRAM or DRAM, depending on the context, but today is most likely
> > > also SRAM.
>
> > Another big difference between SRAM based on-chip RAM and SRAM based
> > on-chip cache is associativity, update/replacement policy support etc
> > all of which makes the cache much more complex.
>
> > /JoachimS
>
> Yes I know; but please refer to Renesas microcontrollers having on-
> chip RAM and Cache. What I want to know is; if the RAM and Cache both
> are implemented using SRAM; then why in some architectures they co-
> exist. Does the size of memory also effect the latency?
> Regards

Well, this setup is also common in many SoC designs, for example with
ARM and MIPS cores. What you have is cache memories that are
transparent to the SW and handled by the CPU HW for updates. Basically
your normal cache memory.

Then you have the on-chip RAM. This memory is addressable by the SW,
that is it is part of the normal memory address space. Some of it
might be external and some of it is internal. This type of memory is
sometimes called a SW-controlled cache, which basically means that it
is the responsibility of the SW (OS or application) to utilize this
memory. Some common usages for this type of memory is to place IRQ-
handlers there. Since you have low and fixed latency to the on-chip
mem IRQ-routines, timing critical stuff benefit from these memories.

When it comes to latency, you often find that the on-chip cache
memories (esp L1) are faster than on-chip RAM. This is due to the
implementation. One uses larger registers for the small cache, and it
is physically located near the CPU core to remove any transport
latency. Big on-chip (L2, L3) caches are basically at the same latency
as the on-chip SRAM. BUT the caches might still have more than one
port to allow simultaneous read/write operations. The on-chip RAM is
generally a simple SRAM array with one port connected to the on-chip
system bus. AHB, AXI, etc.


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