FPGA

Synplicy and Xilinx - no PAR
I've got major issues here. I've installed Xilinx 9.2i with the latest updates and service packs, and am trying to get Synplify 8.9 to actually work with it. The problem is that although I can compile my code fine, when it comes time to start the Place and Route state, nothing happens. I know my project files a... 28 Jan 2008 05:25

Xilinx Spartan 3A/DSP with Coregen 9.2i?
I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.) When I ran Core Generator 9.2i.04 (with IP Update #2), created a new Spartan3A/DSP project, then looked at what wonderous DSP-blocks I could add, I discovered almost everything fun is greyed out. Basically, the IP-Cores haven't been updat... 27 Jan 2008 01:00

buying fpga kits in denmark
Hi , Can anybody give me some information on buying fpga kits in denmark? ..iam interested in the altera cyclone 3 starter kit! .,guess its possible to order from Altera directly , but i might have to deal with the import procedure myself ...I tried farnell elektronics denmark (http://dk.farnell.com/jsp/home/hom... 27 Jan 2008 07:55

Thoughts about memory controller problems
Hi, I tried to boot Linux on my FPGA-prototyped SoC system. The Linux image is running from SDRAM which is controlled by a Dynamic Memory Controller, but the Linux boot always stop at somewhere around(not at the same point each time): Mount-cache hash table entries: 512 <6>CPU: Testing write buffer coherency: o... 28 Jan 2008 18:48

Endpoint Block Plus v1.5 example design
Hello, I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core with ise's coregen and compiled the smartmodel libs also with with ise. But when starting the simulation the following happens: ncsim: 06.11-s002: (c) Copyright 1995-2007 Cadence Design System... 25 Jan 2008 12:14

Endpoint Block Plus v1.5 example design
Hello, I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core with ise's coregen and compiled the smartmodel libs also with with ise. But when starting the simulation the following happens: ncsim: 06.11-s002: (c) Copyright 1995-2007 Cadence Design System... 25 Jan 2008 12:14

OV7660 CMOS camera
Hi all, Am working with this camera. wanted to know if anyone else has worked with it before. I have a set of register settings and want to know if that is right. i am working towards getting a RGB 555 VGA 640x480 configuration here is the register settings. 0x12, 0x80, 5ms delay 0x11, 0x81, 0x9E, 0x3f, 0x... 25 Jan 2008 11:40

Fixedpoint Multiply/Accumulate in DSP48
Hi, am a little confused as far as the capabilities of the DSP48 go. I would like to implement a 18x35 MACC in (hopefully) only two DSP48. The 18 bit coefficient is a 0.18 fixed point number. I.e. what I really want to implement is ((A18 x B36)>>17)+C48 Apparently I overlooked that the DSP48 slice only allow... 1 Feb 2008 18:40

Initialize RAM in IGLOO
Hi all. I am making a design for an IGLOO FPGA from Actel and I have have added a Two Port RAM component in Libero (the development tool). Here I can choose to "Customize RAM Content" and have imported an Intel Hex File. This works perfectly in simulation, but not post-synthesis and layout simulation. Ca... 25 Jan 2008 09:59

Craignell FPGA DIP Module
Craignell user manual is now available http://www.enterpoint.co.uk/component_replacements/CraignellUserManualIssue1_00.pdf. We also have UCF file available for the CR40 and the other sizes to follow shortly. John Adair Enterpoint Ltd. ... 28 Jan 2008 19:56