FPGA

equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix II GX-90
On Jan 28, 2:52 pm, "chaitanyakurm...(a)gmail.com" <chaitanyakurm...(a)gmail.com> wrote: i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II GX-90 in terms of the resources available in these devices (logic, block ram, ... 1 Feb 2008 00:43

Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?
Has anyone succesfully used Aldec Active HDL 7.3 (web-eval) with a (Verilog) Smartmodel simulation? I'm using Xilinx Webpack 9.2i.04 (IP-Update#2), and I separately downloaded and installed the Aldec Verilog library-update for 9.2i.04. In Coregen 9.2i.04 (IPUpdate#2), I created a Verilog Virtex5/LXT50 TEMAC. ... 1 Feb 2008 00:43

regarding DMA memory to memory copy in NIOS II
here is my codes. I want to verify the result and display at the end, however I got like "cdcd", what's wrong? thanks /* * "Hello World" example. * * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example * de... 1 Feb 2008 00:43

Power Supply Bypassing Presentation
Hi - Power supply bypassing being a hot topic in these parts, some folks may be interested in the following. According to the IEEE Santa Clara Valley IEEE EMC web site, Steve Weir of Terraspeed Consulting will be giving a presentation titled, "Using a Spatial View to Understand and Solve Common Power Bypass Pr... 28 Jan 2008 15:56

My first Flash FPGA
Hi all, I started a book witht that titled in 2006, but never finished, as I found the sources now, well it is still unfinished, but maybe it brings some smiles onto the faces of some FPGA developers, so am making the "unfinished" version available for direct download. http://www.truedream.org/smile/MyFirstF... 1 Feb 2008 00:43

equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix II GX-90
i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II GX-90 in terms of the resources available in these devices (logic, block ram, dcms, global clock etc) with those available in Xilinx FPGAs. thanks ... 28 Jan 2008 04:51

Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's Systemverilog support was quite far behind Modelsim 6.2g. Now, I was wondering how these two products compare, today. Looking at Aldec's online manual, it seems Active-HDL 7.3 has caught up wit... 1 Feb 2008 14:13

Call for Papers: The 2008 International Conference of Signal and Image Engineering (ICSIE 2008)
CFP: The 2008 International Conference of Signal and Image Engineering (ICSIE 2008) From: IAENG - International Association of Engineers Draft Paper Submission Deadline: 6 March, 2008 Camera-Ready papers & Pre-registration Due: 31 March, 2008 ICSIE 2008: 2-4 July, 2008, London, U.K. http://www.iaeng.org/WCE2008... 27 Jan 2008 13:35

Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)
Hi *, since switching to ISE9.2, one of my favourite topics has come up again... Basically, what I have is an FPGA with a bank that has a VCCO of 3.3V. This bank has several LVTTL outputs and a few LVDS25-inputs. At the time when the board was designed, this was a valid configuration: LVDS-input buffers are powe... 29 Jan 2008 02:38

FA: Brand New Altera MasterBlaster up on Ebay
No reserve. ... 27 Jan 2008 09:37