FPGA

new to NIOS II
Hello group, Recently I have started to learn NIOS. I will appreciate it if somebody knows any good online resource or book that I can use. Thanks, Amit ... 1 Feb 2008 00:43

About 10-bit pixel datum from CMOS image sensor
Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am using a Spartan3 starter board to interface with a Micron CMOS Image sensor (MT9T001), and is confused with the output data from the sensor. It outputs 10-bit pixel datum in each pixel clock, but I am ... 1 Feb 2008 00:43

Xilinx prom programming problem
I have a custom board with a V4 LX60 and a XCF32P config prom. I can config the FPGA directly via JTAG, but I cannot program the prom. I hope someone can point out the stupid mistake I'm making. I am using ISE ver 8.1 and a parallel cable 4. The two devices (fpga and prom) are in a single JTAG chain, with the ... 1 Feb 2008 00:43

EPC in Xilinx EDK 9.2
I use External Peripheral Controller to access various peripherals from my MicroBlaze/PPC based systems. To allow access to slow serial off-chip peripherals I always set C_PRHx_RDY_WIDTH long enough to suppress bus timeout before peripheral is ready. I never had problems with opb_epc in EDK <8.2. My recent design i... 1 Feb 2008 00:43

PC requirements for ISE webpack
I am thinking of buying (or upgrading) my PC for an FPGA project. At the moment I am using a windows laptop for synthesis and P&R runs. I use a Linux PC for simulation runs. Ideally I would like to move everything onto a linux PC. I have not got to the stage of debugging the design. I would say I need a PC... 1 Feb 2008 00:43

ROM/LUT
I'm trying to understand the intricacies of implementing a ROM in an FPGA. I've searched around and come up with some useful tidbits, but I was hoping someone here could clear up a few issues with doing it "right" for those looking to learn. I would greatly appreciate any comments on the "correctness" of the follow... 1 Feb 2008 00:43

Regarding Hyperterminal
Hi, I have a quick question, and its been bothering me for at least 3 hours. So I made a project in EDK, and I simply want to run the memory test (powerpc). When I followed all the steps (generate bitstream, download bitstream,etc), the code seemed to be fine, because it showed "programmed successfully" in th... 1 Feb 2008 00:43

question on record types
I have defined two functions as below function complexMult (a_i,a_q,b_i,b_q: signed) return complex is variable a,b : complex; variable result : complex; begin assert a_i = a_q report "Error : complexMult - a_i and a_q are not of equal length." severity error; assert b_i = b_q report "Error :... 1 Feb 2008 00:43

difference between net skew in the clock report and clock skew in trce log
On Wed, 30 Jan 2008 02:25:35 -0800 (PST), michel.talon(a)gmail.com wrote: Hi all, I've something strange in my design... I think there is something I don't understand.. I've a clock distributed on a global clock network, It seems to be ok.. In the "Clock report" from the ISE PAR, I can read a "net ske... 1 Feb 2008 00:43

difference between net skew in the clock report and clock skew in trce log
Hi all, I've something strange in my design... I think there is something I don't understand.. I've a clock distributed on a global clock network, It seems to be ok.. In the "Clock report" from the ISE PAR, I can read a "net skew" of 0.276ns and a max delay of 1.779ns (I'm using a virtex5 XC5VLX50). But when... 1 Feb 2008 00:43