FPGA

Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation Problem
I installed the 10.1 ISE Webpack. The pack installed successfully except for the driver. I have found(http://www.rmdir.de/~michael/ xilinx/) that in 10.1 the driver is prepackaged. I enabled the environment variable(XIL_IMPACT_USE_LIBUSB to 1) and tried to reinstall the driver. This resulted in the same error as be... 2 Apr 2008 12:17

Xst_Choice nodes
Hey, Im trying some synthesis with Xilinx Xst in ISE 9.2 and i'm getting this error ERROR:Xst:2259 - Unit <chip> has internal Xst_Choice nodes Anyone know what an Xst_Choice node is? I've no idea what it is - maybe something to do with my coregen cores? Can't find an explanation for ERROR 2259 anywhere ei... 2 Apr 2008 10:04

"Number of BSCANs: 2 out of 1 200%"
Hi, I have added Chipscope to my design, but it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of 1 200% (OVERMAPPED). The reason is that I need to use OPB_MDM since I have to download the executable.elf. I have read that it is possible to use OPB_MDM and Chipscope if they share the BSCAN. C... 4 Apr 2008 03:36

coregenerator bram in synplify pro error
I am trying to get rams in xilinx to synthesize in synplify pro. I am a novice in syplify pro. I used the core generator to generate BRAM and then since for brams we cannot generate edif files I used ngc2edif to convert it to .ndf. I then added these ndf files into the project. Howewver I seem to get an error with ... 3 Apr 2008 21:59

ISE 10.0 finally with multi-threading and SV support ?
On Mar 19, 4:20 am, ratztafaz <heinerl...(a)googlemail.com> wrote: What other major features to you still miss? - Discuss! Oh, let's see: a) When you include an EDK project (.xmp) in your ISE project, the tools should be smart enough to know that the external ports in your .mhs file should NOT synthesize to ... 1 Apr 2008 19:34

Why does ISE 9.2 optimize out the logic
Hi, I want to use RLOC function of ISE 9.2. I find at the end, all logic are optimized out, see below the simplest example. I can see the results after synthesis are correct. How to avoid this? Thanks in advance. --------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use... 1 Apr 2008 17:21

now I can talk about it...
http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 Ta Da! Austin ... 2 Apr 2008 09:31

ISE 9.2i project question
When i add existing source files ISE copies them to the project directory but i want to use them in their current directories (by reference). It's a small point but i cant seem to find out how to do it...... Is there a box I can tick somewhere saying Do Not Copy Source To Project Directory? Cheers :-S ... 1 Apr 2008 11:46

Antii, can you give us an update?
I've read all the posts here but have lost track of how you're getting on. Can you post an update and describe what the problem turned out to be? Nial. ... 7 Apr 2008 11:27

Simple (?) timing constraint for output pins
Hi *, I am driving a bunch of DACs each having its own SPI bus with a Virtex4 FPGA. The test design is up and running fine (generating a sine output via an DDC generator implemented on the fabric). Now I want to make sure it still works fine after the FPGA is stuffed with more control logic. The DACs have both... 2 Apr 2008 04:21