FPGA
in [Hardware]
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Power Estimation of Microblaze (Power PC) based architectures On Mar 26, 4:24 am, Philip Potter <p...(a)doc.ic.ac.uk> wrote: ahosyney wrote: [Powerestimationusing XPower and ModelSim] To Clarify this I started with an array size of 10 integers, this array requires 887 clock cycles to be sorted and the total estimated powerconsumption was around 488.65 mW. ... 3 Apr 2008 12:52
Spartan3 JTAG flash In System Programming over Ethernet I am interested in using the Xilinx 10/100 Ethernet solution supported in their Spartan3 eveluation kit. I have a JTAG based flash PROM XCF02S connected to the Spartan3. I would like to know best way to do the In System Programming of this JTAG based PROM over the ethernet. The Xilinx reference design for the 10/... 9 Apr 2008 11:20
Beginner's silly question about ICAP Hi Comrade, I run into troubles trying to read anything using ICAP. I set "-g security:none", just in case. When I try to read for example STAT Register, BUSY goes HIGH when I switch to reading and stays that way. I deselect device (i.e. assert CE to HIGH) first then toggle WRITE. Output O[7:0] is set to ... 4 Apr 2008 04:44
Protecting design from being downloaded on other (similar) FPGA devices All, Possible solutions exist today for Virtex II, IIP, 4, 5: use encryption. Only the device with the proper key configures. In Spartan 3A, 3AN, 3ADSP, there is the "DeviceDNA" feature which may be used to identify a specific device. This identification requires a customer design to provide the function... 8 Apr 2008 04:52
Protecting design from being downloaded on other (similar) FPGA devices Hi, I need to know how can I prohibit a configuration file from being downloaded on a similar FPGA device. For example, if I have two similar FPGA boards and I want only one FPGA board to be successfully programmed with the configuration file whereas if the same configuration file is downloaded on the other FPGA b... 6 Apr 2008 21:48
EDK 10.1 first impressions Hi here it goes: I got last week new notebook that is faster then the desktop, so I installed 10.x tools there. And I had a small task to verify something with ML505, so I fire up EDK 10.1 open the ML505 reference design, and within 3 minutes EDK self-terminates. So TTFFF (time to first fatal failure) 3 min... 4 Apr 2008 21:53
Conterfeit parts guidance Hello all, I am a Quality manager at Xilinx, and I have asked to provide specific guidance on the question of counterfieting. I would like to start by saying that the ONLY way to protect yourself is to purchase your devices from an authorized Xilinx distributor. A list can be found at this link. http://www.x... 8 Apr 2008 13:14
counterfeit Xilinx ? On Mar 27, 10:19 am, Jon Elson <el...(a)pico-systems.com> wrote: Georg Acher wrote: Jon Elson <el...(a)pico-systems.com> writes: Georg Acher wrote: I have XCS10XL in TQFP100 from around 1999/2000 and they also have printed labels. They were obtained from the official German distri at that tim... 22 Apr 2008 21:12
ModelSim XE problems with a VHDL coregen in a Virtex 5 I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be used. I see these files in the $XILINX\vhdl\src\XilinxCoreLib directory, but they do not show up in the ModelSim workspa... 4 Apr 2008 06:58
Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation ?Problem disq <rettura(a)gmail.com> wrote: I installed the 10.1 ISE Webpack. The pack installed successfully except for the driver. I have found(http://www.rmdir.de/~michael/ xilinx/) that in 10.1 the driver is prepackaged. I enabled the environment variable(XIL_IMPACT_USE_LIBUSB to 1) and tried to reinstall the dr... 2 Apr 2008 12:51 |