FPGA
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Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin) "austin" <austin(a)xilinx.com> wrote in message news:ftg25m$p2m2(a)cnn.xsj.xilinx.com... Intel has also been working very quietly on this, with much less press. Hi Austin, I wondered what were your thoughts on their patent where "The cosmic ray detector [built into the device] is therefore designed to spot w... 18 Apr 2008 06:48
Intel plans to tackle cosmic ray threat (actually they have beenworking on it for at least five years...austin) Symon, Well, Cypress, Xilinx, IBM, and many others have made it no secret that neutrons at sea level are causing upsets, and we have done something about it (and presented the papers, and shown our results). Intel has also been working very quietly on this, with much less press. I suggest that if you are not... 11 Apr 2008 11:53
Intel plans to tackle cosmic ray threat Dear All, Austin in particular, I saw this and thought of you! Cheers, Syms. http://news.bbc.co.uk/1/hi/technology/7335322.stm ... 9 Apr 2008 13:49
NoisII or else. Hi, Simple question. Can I put a NiosII on an FPGA alone, no ROM no DRAM no SRAM no nothing, Just the FPGA ? (examples and kits put me on the opposite extreme) I understand that I would have little ram space etc... so programs will be small... etc etc... I just wonder if it is feasible and how to load al... 9 Apr 2008 10:32
OBUF gate delay Hi, I am using virtex4 device for my designs. In timing analysis i found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is that a way , i can reduce this gate delay by giving some constraints. ie is to reduce the gate delay by tools . ... 8 Apr 2008 10:48
MIG/Corgen to XPS core insertion Hello all, I am creating at MIG a external DDR2 Memory controller. Then i am trying to add this core to an XPS design. This controller i want to be attached at the PLB bus. When i am going to import peripheral from XPS my created core signals does not interface in total number with the PLB's ones. I... 14 Apr 2008 08:08
Avalon Bus <-> Wishbone Bus I'm pretty new to fpgas, but theres an i2c core on opencores.org that I'd like to use in my Altera project. I understand Wishbone is a subset of Avalon, but what is involved in bridging these two together? I'm assuming its not too trivial since I could buy an IP bridge that does it from Men Micro, but what exac... 8 Apr 2008 01:13
Modify POF with new ESB (ROM) content? Hello, We have a design that has an embedded PIC processor that uses ESB's for instruction and data RAM. The target is an Altera APEX 20K100 with an EPC2 configuration PROM. What we would like to do is download the current POF from the configuration PROM and update the instruction ROM with an updated version. W... 9 Apr 2008 08:54
FPGA configuration mode on ML310 Hi! everyone I have a very basic problem. I know that the 6-position DIP switch on the ML403 board can control the configuration address and FPGA configuration mode. On the ML310 board, I am not sure where can set the FPGA configuration mode. I want to set the configuration mode of my ML310 borad as the SelectMA... 8 Apr 2008 22:06
19th IEEE/IFIP Rapid System Prototyping Symposium ------------------------------------------------------------------------- Please, feel free to forward this message to interested people. We apologize if you receive this email more than once. ------------------------------------------------------------------------- Call for particip... 7 Apr 2008 04:17 |