FPGA

64 bit WebPack
Will there be a 64 bit WebPack version of ISE in the near future? Rog. ... 16 Apr 2008 05:48

Xilinx tech Xclusive
What happend to the tech Xclusive articles that used to be on the Xilinx home page? I was trying to find one of Austins excellent articles on synchronous digital design but where unable to locate it... ... 14 Apr 2008 21:00

Xilinx ISE synthesis error (error:3524 Unexpected end of line.)
Hello, when trying to synthesize a VHDL file (part of a design) that has already been compiled and simulated by Modelsim, ISE gives the following error: " ERROR:HDLParsers:3524 - "G:/des1/chsam_struct.vhd" Line 132. Unexpected end of line. " It refers to the last line of the following code, any idea what... 11 Apr 2008 06:05

Split register in smaller segments
Hi, I'm working on a little UART to get more familiar with verilog, and right now I have the following input: parameter width = 32; /* Must be multiple of 8 */ input [width - 1: 0] iData; /* number of characters to send for each piece of data - 1 */ parameter chars = width / 8 - 1; The iData first goes i... 11 Apr 2008 06:52

Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the module with the generated xco, I am now trying to simulate the module. The hierarchy is as follows: fft_tb => fft_top => fft.v (generated by coregen) I am using a custom script... 11 Apr 2008 08:41

why to trigger a NMI error after just receiving 35 pakcets?
My PCIE device is a Gigabit NIC. The lnx ifconfig command can show the tx/rx packet count from this NIC. after loading lnx driver,it will be triggered a NMI error only if ths rx packet count reaches 35.The system isn't be halt,however the NIC doesn't work. it is regardless of the packet size.eg:i send the ping cmd... 11 Apr 2008 05:17

clock instanciation
Hi, in my book it's written that the clock has to instactiated like this : architecture Behavioral of fftest is constant T : time := 20ns; .... begin .... --clock process begin clk <= '0'; wait for T/2; clk <= '1'; ... 10 Apr 2008 12:55

Specifying strict setup constraint in ISE
Hi All, I need to specify the strict setup time for the group of signals. It can be relatively high, but I need very low skew between the signals. In Quartus for Altera FPGAs I can define it with the sdc contraints as follows: set_max_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 6.000 set_min_delay... 10 Apr 2008 11:18

Xilinx FFT C-sim model
I've noticed that the Xilinx FFT bit-accurate c simulation calls are very very slow. Anyone else notice this? I am working on hybrid fixed/floating-point digital signal processing application, and I frequently make calls to the bit-accurate simulation function (anywhere on the order of 1,000 times, to 1,000,000... 11 Apr 2008 10:17

Xilinx CPLD programming tool under Linux
Hi all ! I'm wondering if a basic tool already exist to program Xilinx CPLD (XC95144 and so) under Linux (preferably with the old Parralle cable III) Thanks, Habib. -- HBV ... 10 Apr 2008 15:19