FPGA

Question about Spartan 3E starter kit
Hi there - I'm very new to FPGAs and so I'm probably doing many dumb things. I recently got a Spartan 3E Starter Kit (http:// www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable). I followed the guide shown here: http://www.fpga4fun.com/ISEQuickStart.html to make a new project. Whe... 13 Apr 2008 19:09

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Spartan3E startup problems
i got a problem with the Spartan 3E starter kit from Xilinx, no matter what Mode pins are set for, the DONE LED is always turned on when i power on the board. I cannot connect to the board via JTAG pin headers either. All the voltages are correct. What could be the problem ? any thing i can do to debug it ? i have ... 14 Apr 2008 00:43

simple example with timing problems
Hi, I wrote a simple stop watch for the Spartan 3 StarterKit. Unfortunately it seems to be unstable, i.e. sometimes when I release the button, the counter doesn't stop as it should. During synthesis I get a warning - about timing I think. Can you have a look at the program and advice me how to avoid this instabil... 12 Apr 2008 15:05

CF (systemace) SD card, etc performance
Hi I was recently very disappointed with the performance of Xilinx systemACE, but the problem was in my head, a thinking problem and too little homework - the issue is not related to systemACE or CF cards, but it is present by almost all flash cards - the "controller overhead" very short: any flash-card (exce... 13 Apr 2008 03:47

Need help on UNISIM.Vcomponents.all
Hi, I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera. I use only a few components from the unisim lib so may not be a big effort to write a vhdl component for each one of them, providing I know the details what they do exactly. Can someone... 14 Apr 2008 06:17

high noise/signal in a simple serial to mono dac module
Hello I am working on playing simple 11 kbytes/second 8bit WAV data through my FPGA stereo jack. I used the following synthesis to play the sound data delivered through the serial interface. I also used the mono_dac demo module. My problem is I am getting a very high noise to signal ratio although I can hea... 13 Apr 2008 02:11

Virtex4 FX PPC and Fsl
Hi, I have the following problem: I have designed a peripheral with a Fsl bus. It works fine when I create and EDK Project with micoblaze. Now I wanted to switch to a Virtex 4 with a Power PC. I know the there exists and Fcb2Fsl bus brigde. I searched the xilinx web site and google for some examples or tutoria... 11 Apr 2008 15:54

ISE 9.2 and Windriver
Hi, my Windriver trial period has expired, and then I found out that the license costs $900 ?!? Is it possible to bypass windriver - e.g. by using the xilinx usb-cable ? I'm currently using the Digilent parallel cable. Best Regards Thorsten ... 12 Apr 2008 15:53

case statements- verilog to vhdl
I have the following scenario in verilog which i need to convert to vhdl always if reset .. .. .. else case . . . end case // set default values case. . . . . end case end How do I convert this to vhdl. I am lost on what the equivalent of // set default values and the case stat... 14 Apr 2008 19:25