FPGA

Pre and Post Synthesis Simulation mismatch
Hey everyone, Im having difficulty with signals that i tie to zero or one (using Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation. They appear fine in pre synthesis simulation, as one or zero depending on what i specify, but they always appear as z in post synthesis simulation. As a resul... 15 Apr 2008 13:09

Simulation tools for Xilinx ISE
Howdy - I'm just getting started with FPGAs. In college I remember we used ModelSim with ISE for FPGA simulation. We were able to get a license through our school for free. Like a fool I no longer have that license, so what free options are out there? I saw that there is something called ModelSim Xilinx Edition III... 18 Apr 2008 13:26

Xilinx JTAG Linux programming
Hi all ! i have been installing "libusb-driver.so" found here http://rmdir.de/~michael/xilinx/ and it simply work fine with PCIII I also recommend to read documentation on the web site and inside the source package. Thanks to Uwe ! HTP, habib ... 15 Apr 2008 03:22

"Multi-source in Unit" Verilog synthesis woes
Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although not to programming in general. So far the FPGA design work has been going smoothly enough, but I'm having some trouble with synthesizing the code I wrote for my DAC. I tried to avoid all of t... 14 Apr 2008 17:49

DOS script file to synthesize a VHDL design
Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding something from: http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/xst/xst.pdf But I still need more help. Can someone please tell me the sequence which I should follow. Thanks ... 15 Apr 2008 15:38

Actel Cortex
Hey, Does anybody know if there is a port of Linux on the ARM-Cortex on Actel ? Thanks, John ... 14 Apr 2008 15:24

Which to learn: Verilog vs. VHDL?
Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer by training and did some verilog in my collegiate days - but that was quite some time ago and it is all very fuzzy now. I have decided that as an EE I should be familiar with FPGAs - so I'm re-edu... 18 Apr 2008 19:02

Chipscope 9.2 in XPS
Im trying to include a chipscope core into XPS 9.2 using the Debug configuration screen. When i set up the core and try to update bitstream i get following error: ERROR:MDT - chipscope_icon_0 (chipscope_icon) - Generating the core : chipscope_icon_0.... Chipscope Core Generator Error : Unable to find t... 14 Apr 2008 08:08

XST support for User Defined Primitives
Hi, Does anyone know if user defined Primitives are supported with XST, I have the following code and it is giving error, primitive mymultiplexer (y, a, b, c0, c1, c2, c3); output y; // reg y; input a, b, c0, c1, c2, c3; table // a b c0 c1 c2 c3 y 0 0 1 ? ? ?... 14 Apr 2008 12:10

HiTech Global Eval boards?
Hello I need a large Virtex-5 FPGA like the SX95T on a PCIe board with DDR2 memory. HiTech Global has a variety of boards with these features but I rarely here that company mentioned on this newsgroup. Does anyone out there have experience with HiTech Global eval boards? How is their quality and documentati... 15 Apr 2008 11:32