FPGA

New to FPGA : Timing Closure
Hi All, I am new to FPGA development , I have encountered a timing closure problem and would appreciate some advice from experienced xilinx guys. My problem is as follows - My system has three major modules - 1) Microblaze - interfaced with an external Flash and SDRAM.(using EMC IP core). 2) Ethernet Int... 18 Apr 2008 13:26

Chip photos of old FPGAs
I recently found a couple of XC2018 in a drawer. Although these will probably never see any use again it got me thinking that a chip photo of these chips will probably look pretty nice. Has anyone seen such a photo somewhere? My guess is that it will probably look rather impressive as older chips usually allows... 18 Apr 2008 02:03

XST design frequency setting
Hey everybody, Just started using Xilinx XST as my synthesis tool and I'm just looking for the command line instruction (or GUI) to set the design frequency, I was using precision where it was "setup_design - frequency=66". Anyone know the equivalent command for XST? My eyes cant seem to find it in the docu... 17 Apr 2008 19:43

Survey: FPGA PCB layout
Does anybody out there have a good methodology for determining your optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? The brute force method is fairly maddening. I'd be curious to hear if anybody has any 'tricks of the trade' here. Also, just out of curiosity, how many of you do your own PCB l... 25 Apr 2008 02:58

attached a 2nd peripheral to FSL bus. how to use it in software?
Hi, does anyone know how to use a 2nd FSL peripheral attached to microblaze? This is what I did. I have attached 2 peripherals, let's say we call it peripheral1 and peripheral2 to the microblaze's FSL bus. now here comes the problem. Using the commands putfsl(val,0) and getfsl(val,1), I am able to write and ... 21 Apr 2008 20:33

UK Embedded Masterclass
A few places left - Embedded Linux Workshop, UML, GUI Development, etc etc.. www.embedded-masterclass.com ... 17 Apr 2008 11:44

DMA in PLB custom core (XilinxV4)
Hi, I´ve problems with my custom IP core with simple DMA capability (Master on PLB). The DMA transfer from the core´s BRAM (32bit wide) to Memory does not work properly. Every second word is missing. With direct BRAM access it works well. Does anybody have any ideas? Thx in advance. ... 17 Apr 2008 10:08

Help, router can't rout all connections (XILINX)
I need help. I get this error when I rout my design for my spartan 3: WARNING:Route:438 - The router has detected an unroutable situation due to local congestion. The router will finish the rest of the design and leave one or more connections as unrouted. The cause of this behavior might be putting too m... 17 Apr 2008 08:33

how do I test signals in a testbench that are 1 or 2 levels downin the UUT?
Dan K wrote: .... if(UUT/instance_1/txcomstart /= '0') then error <= x"0103"; end if; I've tried just about everything I can think of and nothing seems to work. Maybe google for a vhdl testbench example to get started. Here's one: http://home.comcast.net/~mike_treseler/test_uart.vhd ... 17 Apr 2008 15:45

how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
There has to be a way to do this, right? If I want to test a signal in the UUT, I just have to do this in my testbench: if(txcomstart /= '0') then error <= x"0103"; end if; But what if the UUT contains an instance, instance_1 (instance.vhd) and the signal I want to test is in there? I ... 17 Apr 2008 15:45