FPGA

Problem writing quadrature decoder
Hi there - I am continuing to attempt to learn VHDL this weekend! Currently I'm trying to interface to the quadrature encoder on my Spartan 3E Starter Kit. It outputs normal quadrature signals. So, I tried to write a very simple bit of code for this purpose, which just checks which edge on which signal occurred and... 6 May 2008 23:24

synchronous reset problems on FPGA
Hi, I am wondering if anyone of you have experienced this before. Here goes the reset problem I am facing now. asynchronous reset in FPGAs are usually a big NO-NO. from the articles I am reading, the async reset, normally results in more logic being used to stitch up LUTs together. However, the design I am c... 22 Apr 2008 13:12

how we can prove that really the AES 256 is used to crypt the Bitstream in virtex 5
As my current project is about the security that Xilinx embeds in the Virtex 5 , i have some points that i couldn't understand and really i need help to advance in my project : - first how we can prove that really the AES 256 (cbc mode) is used to crypt the Bitstream +> is it possible to know this by taking ... 20 Apr 2008 10:48

Very simple VHDL problem
Hi there - I am slowly teaching myself VHDL this weekend. I am getting an error that I do not understand: "parse error, unexpected IF". My very simple code is at the bottom of this post, and the error is being caused by the "if switches(0)=0 then" line. Can somebody tell me what I'm doing wrong? I'm sure it's terri... 22 Apr 2008 06:19

Synthesis Comparison
Hello, I am writing my report on a university project. The project work involved an FPGA implementation of a neural network. I have created two versions of the design; a serial and a parallel version. Both synthesise and work in hardware. I am comparing the two in terms of performance. I would also like to ... 21 Apr 2008 11:42

Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
In article <3023a7dd-d8cc-40ec-9cc5-8d22b17ea2ec(a)c65g2000hsa.googlegroups.com>, John Adair <g1(a)enterpoint.co.uk> writes: |> Distributors nowadays are pushed to fairly tight margins so you may |> find won't a lot of interest in a low volume, low value, projects. |> Digikey mentioned elsewhere is good if you are in ... 19 Apr 2008 13:55

How to instantiate macro in verilog
Dear all, I've designed a macro, and put "ring.nmc" file in my project dir. In my verilog module file, I wrote .... ring r1(.en(en),.ro(ro)); .... to instantiate ring macro, but failed. Any one could give some hint? Thank you! ... 25 Apr 2008 01:23

Xilinx DDR2 Interface
I used the latest version of MIG to generate pinouts for a Virtex 4 DDR2 interface. In addition to all the usual Address, Data, and Control I/Os, MIG assigned an I/O pin for a signal called SYS_RESET_IN_N. What is the function of this pin? ... 21 Apr 2008 20:33

Has anyone dealt with Avnet? or NuHorizons when trying to purchaseXilinx stuff
Raban wrote: Like what do you have to purchase, software or hardware or what dollar amount to do you have to purchase just to get few questions answered, sales wise for pricing or even worse, tech support? Distributors are order takers. I don't call them until I know what I want. Example: "I would li... 18 Apr 2008 22:14

Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
Hello, I am new to this FPGA stuff and I wanted to purchase a starter kit and get volume pricing for a few Xilinx FPGA's If one where to buy through Avnet or maybe NuHorizons, would anyone like to share your past experiences when working with them? It seems all they care are who you are, what company you w... 19 Apr 2008 13:07