FPGA

Altera Cyc II config problems
Subject board has two 2C devices and a 3C device in a serial config chain. The 2C device's MSEL pins are jumper configurable to AS (for "self-config") or PS ("Software Config") config mode. The other two FPGAs, downstream from the first 2C device, are strapped for PS mode only. A MAX-II CPLD sits on the DCLK, ... 22 Apr 2008 00:36

Newbie: Testbench question
Hello, I have a question about instantiating a module in a verilog testbench. Sometimes the instantiation may have lots of inputs and output that you may not want to appear in the ModelSim simulation, is there a way to stimulate particular signals in a module so the simulation won't include (display) all of the i/o... 22 Apr 2008 11:36

Turning off the DLL to run DDR2 at very low frequency
Hi, There's been a few discussions about this the last couple years, but it seems nothing ended with firm conclusions. What I would like to do is to run DDR2 at 25MHz (DDR50). I understand that to do this I have to turn off the DLL (which can't work at below 125MHz) and that this should work but is not supported... 24 Apr 2008 15:03

opb_intc + PowerPC
Hello. I have a problem with use opb_intc in my projekt In mhs: # External Interrupts PORT IrqSecond_pin = IrqSecond, DIR = I, SIGIS = Interrupt, SENSITIVITY = LEVEL_HIGH PORT IrqPci_pin = IrqPci, DIR = I, SIGIS = Interrupt, SENSITIVITY = LEVEL_HIGH PORT IrqFrame_pin = IrqFrame, DIR = I, SIGIS = Interrupt, SE... 23 Apr 2008 06:43

not inferred RAM, on QII
Hi, On some pretty obvious piece of VHDL (below) QuartusII does not inferred any RAM !!!!!! (whatever "width" value is...) Any help how to convince QII to use RAM and not LEs ??? (all ram options are set to ON... and I've seen it working well on other occasions so what Is wrong here ?) many tks. lc. ... 24 Apr 2008 07:38

DCM configuration in Virtex-4 FPGA
Hi all, I'm having a little problem to implement a DCM. It's the first time i need it (to be able to use DDR SDRAM). Before i'm going to think about a design for a memory controller, i first want to verify that i'm able to control a DCM. I've read a lot of datasheets, and think i know the theory. In ISE 9.2i i a... 24 Apr 2008 03:40

Celoxica RC1000
Hi All i am new to FPGA's and have picked up a celoxica rc1000pp (virtex 2000e) cheap, the downside...no manuals or software. i expected that (being an old bit of kit) the drivers and manuals would be easy to get hold of....oh how i was wrong does anyone on this mailing list have any details on the board... i ... 21 Apr 2008 17:21

OPB_MDM functionality
hi, this is my question: Is opb_mdm used to load C code (from executable.elf) from SDRAM?. I have downloaded an aplication (executable.elf) to the Sdram. Due to the fault of a RS232 peripheral, I use opb_mdm as uart. This design seems to work fine with xil_printf and standalone powerpc, but it fails when I use p... 21 Apr 2008 06:41

XmdStub fails when connecting via JTAG.
Hi, I would like to know if anyone has received this message when he tries to start XMD. This message appears some times and I have to close Xmd Windows and start again so the message doesn't appear. I use Xilinx Parallel IV Cable and version 8.2 for EDK. Thanks. PowerPC405(1) : ppc405_0 Address Map fo... 21 Apr 2008 05:05

ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
Maia is a new tool which automatically creates HDL(*) testbenches from a vector-style description. The trivial test case below, for example, is a complete testbench for a 4-bit up-counter with reset. The tool compiles a test vector file into HDL output, runs the output and the module sources on a specified simula... 22 Apr 2008 06:19