FPGA

superscalar processor design
Hi I am just wondering if somebody has some good sources for a superscalar processor implementation in VHDL? I have found a lot simple Implementations but struggle to find a superscalar one. Especially the logic design of the dispatcher unit would be interesting for me where the independet instructions are ide... 23 Apr 2008 11:43

FPGA comeback
Hi I want to get into FPGA design after long time I was out of it. I did some work with ALTERRA long ago . I mainly did VHDL models for asic . I want to buy some FPGA board and to do some projects on it with VHDL to get into that field again . My question is which board and which FPGA vendor is reccoman... 25 Apr 2008 00:36

Verilog state machines, latches, syntax and a bet!
Hi, A colleague and I are having a friendly debate on coding state machines in Verilog, targeting synthesis for FPGAs. Comments are very appreciated. I am NOT trying to start a holy war here regarding syntax style (one process vs. two process, etc). Crux of the matter: Do you need to define values for outpu... 24 Apr 2008 15:03

10.1 EDK - How can I create a user library in SDK?
Dear experts, I may need to build a few user libraries for PPC and MBZ targets, the libraries would be hardware independent, just computational modules. I've read this link http://www.xilinx.com/support/answers/29926.htm Does the solution means that I have to manually edit the project's makefile to "make" it c... 23 Apr 2008 04:20

the order in which some switches are turned on
Hi Laura, FPGAs can do what you want, though it might be simpler do solve with a microcontroller. The tricky thing is to define "in the same moment" more technically. If the switches are operated manually it is virtually impossible to have two switches changing their state "in the same moment", even if they ar... 24 Apr 2008 17:27

Can somebody help about Period Timing Constraints
Hi all, I don't understand is there any the relationship between the value of period constraints and my input clock? For my system, Board input clock is 50MHz, system works at 500MHz. When there is no timing constraints: Chipscope result is not right: some signals should be all zero while they show certain pul... 23 Apr 2008 10:55

FPGA Verilog state machine lock up
Hello, I am using Verilog to program a Xilinx FPGA. The program is basically a state machine with at least 32 states. There is an internal counter that counts and allows the state machine to move from one state to the next. This program simulates well both pre and post synthesis and goes through all the states c... 22 Apr 2008 18:01

Xilinx is cancelling the Virtex-E XCV1000E-FG860
Xilinx is canceling the Virtex-E XCV1000E-FG860. We are currently shipping a product that uses 13 of these chips on 4 different boards. Does anyone have any ideas on how to deal with this? One possibility is to rev the boards to use the XCV1000E-FG900, making minimal changes to the boards around the fpga. ... 25 Apr 2008 01:23

Need a few Xilinx Spartan FPGAs
Hello, Does anyone have a few XCS30 -3TQ144C FPGAs around, or know a distributor who will sell in small quantity? I need about a dozen to finish off the last boards using that chip. I've just about finished the conversion to the Spartan 2E but need to use up these last blank boards first. Thanks in advanc... 22 Apr 2008 11:36

How to independently program the embedded PowerPC in a Virtex?
Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded PowerPC independently from booting the whole FPGA via the Xilinx Platform Flash. Is there a way to account for that, maybe be designing an additional Flash device in the BS chain? Is it even... 22 Apr 2008 13:12