FPGA

Aldec Active-HDL 7.3 sp1 [stimulators]
On 3 mai, 04:47, 0xdeadbeef <Przemyslaw.D...(a)gmail.com> wrote: Hi all. I'm brand new in fpga subject so please be patient :P My problem is about to use stimulatorin waveform. Well, exactly- there is no such thing as stimulator as it was in ahdl 7.1. How to add it then ? Please help me because w/o it... 6 May 2008 23:24

BRAM initialization / bitstream configuration
Austin , Exactly what i need ! thank you ! M.B ... 6 May 2008 22:20

Getting started with VHDL and Verilog
Hi all, My background is in Software Engineering C,C++,Java and Unix. I am getting started with VHDL and Verilog. What is the good way/books/ websites/training to get started? I have B.S. and M.S. in Computer Engineering. Also, what is the learning curve in VHDL and Verilog? Please let me know. Thanks Jay ... 7 May 2008 05:53

EDK9.2i simulation problems.
Hi 1) I am having some EDK simulation problems. I am using EDK9.2i with microblaze 7. I have attached a peripheral to the FSL bus using EDK's configure coprocessor and written its corresponding drivers for the peripheral which has commands like the one below. ie.. #include "mb_interface.h" ..... mi... 6 May 2008 23:24

Old FPGA question
Nicolas Matringe wrote: whygee a écrit : Don't ask me that, I'm just looking in the trash bin :-) Yann you'll have to tell me where this is ;-) ok :-) my old f-cpu email address still works ;-P Hint : it's in Paris. btw, i checked my treasure : there are 57 reels of resistors and about 30 of ceramic c... 6 May 2008 22:20

need recommendation for PCB fab & BGA assembly vendor, I'm in SF bay area
Hi. Does anyone have recommendations for a pcb fab vendor and an assembly vendor ? Preferably the same vendor but ok if not. This is for just a few small boards, 6-8 layers, a couple of FPGAs in bga package. I'm looking for quality 1st & price 2nd. Don't want any bad coonections on some power & gnd balls... 6 May 2008 22:20

FPGA dev kit with 4-8 Cyclones or Spartans
On May 7, 12:11 am, austin <aus...(a)xilinx.com> wrote: Why? What is it you are trying to show, prove, or do? It would be nice to know. It is most cost-optimal for crypto-tasks, if I'm correct, of course. Like it was done there: http://www.copacobana.org/faq.html ... 6 May 2008 22:20

Using SRL16 with reset
Alain, Yes, that is a neat feature (allow a set or reset with small overhead while still using SRL), however I have seen a thread where it isn't working as intended for some cases. There is a CR filed on it, so we will see if it is a real bug, or a weird corner case (which still needs to get fixed). Auto... 6 May 2008 22:20

DSP48 Inference Template for XST
I'd like to infer a DSP48 in XST and can't find a template that will infer all of these opmodes: P=M P=M+C P=P+M P=P-M (where M=A*B) I can get XST to do any of these, one or two at a time, but when I try to do all at once it adds a bunch of fabric. Any suggestions? The code below, for example, pr... 7 May 2008 13:24

NGC / EDIF Viewer
Suggestion: if you are using XST (or any other synthesis tool) and have Xilinx's PlanAhead, you can bring in an NGC/EDIF and view the schematic with PlanAhead's viewer. I just started using it and find that it's pretty good. -Kevin ... 6 May 2008 21:27