FPGA
in [Hardware]
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ANNOUNCE: new version TimingAnalyzer beta0.84 available Hello All, A new version beta 0.84 is now available. The following changes and additions have occurred. 1. Added eps,pdf,svg,png,gif,and emf file formats to SE 2. Added bus value button so H L Z and X now work with busses 3. Added IncDecBusValueCommand (increment and decrement use undo/ redo) 4. Add... 22 Jun 2008 20:23
ANNOUNCE: new version beta0.84 available Hello All, A new version beta 0.84 is now available. The following changes and additions have occurred. 1. Added eps,pdf,svg,png,gif,and emf file formats to SE 2. Added bus value button so H L Z and X now work with busses 3. Added IncDecBusValueCommand (increment and decrement use undo/ redo) 4. Add... 22 Jun 2008 20:23
virtex-5: can't use DCM (too low input frequency) Hi all, I have a camera and a Virtex-5 FPGA, and i would like to store frames in FPGA Block Ram. In my design (that worked with Spartan-3E) i need to double camera clock frequency, in order to get all data, because camera send data on both clock edges. The problem is the following: I can't use DCM, because camera... 24 Jun 2008 09:13
Image Sensor Interface. Hi, I am planning to read an image sensor using an FPGA but I am a little confused about a bunch of things. Hopefully someone here can help me understand the following things: Note: The image sensor output is an ANALOG signal. Datasheet says that the READOUT clock is 40MHz. 1. How is reading of an image sensor... 25 Jun 2008 01:40
Call For Participation: WORLDCOMP'08 (CS and CE conferences), July 14-17, 2008, Las Vegas Call For Participation WORLDCOMP'08 The 2008 World Congress in Computer Science, Computer Engineering, and Applied Computing Date and Location: July 14-17, 2008, Las Vegas, USA http://www.world-academy-of-science.org/worl... 22 Jun 2008 10:09
Newbie Verilog Question / ModelSim Hi, I am thinking of using Verilog for a project I am working on. Originally I was going to use a processor core (and C) on an environment someone set up for me in VHDL/Verilog, then I thought of using FpgaC and doing it myself, and now I'm more or less decided on using Verilog to do most of it (minus the ha... 22 Jun 2008 14:15
Altera, Cyclone III, PCI, LVCMOS, & 3.3V Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? I've read Altera apnote AN447 http://www.altera.com/literature/an/an447.pdf I understand this apnote to suggest that any/all 3.3V LVTTL or LVCMOS signals connected to a Cyclone III must employ series terminati... 22 Jun 2008 19:22
Xilinx Clock Doubler On May 29, 8:52 pm, Eric Smith <e...(a)brouhaha.com> wrote: Peter Alfke wrote: ... the "six easy pieces" that seem to be lost. ... The "six easy pieces" article is exactly the sort of thing that I was worried would be lost. :-( ... Eric Eric, Peter, Don't worry! it's not completely lost..... 21 Jun 2008 12:46
help using lwIP with xilinx EMAC hello... in order to interface between my pc (via matlab) and the XUP Virtex 2 pro board, i came to know i'll have to use the lwIP library/stack... is that right? (there is no OS running on the ppc405 in the board, and windows xp on the pc....) should i use the raw API or sockets? also, could you plea... 21 Jun 2008 14:48
ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams In article <LOd3k.9642$Ri.1039(a)flpi146.ffdc.sbc.com>, Vladimir Vassilevsky <antispam_bogus(a)hotmail.com> wrote: rickman wrote: I couldn't figure out how to do a lot of things and I ended up installing Win2000 over it. So what exactly is better about Linux? I second your opinion regarding... 21 Jun 2008 07:39 |