FPGA

XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATIONPORT)
Chetan, What device family? V2P, V4, or V5? Also, there is a serial loopback, and a parallel loopback. And, if that is not enough, are we talking near end, or far end which is looping back? Generally, a parallel or digital loopback checks the function and the logic (step one of any testing). Then a near en... 23 Jun 2008 18:54

XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION PORT)
I am trying to enable an internal loopback in a xaui core (near-end PMA loopback) and would like your suggestions on that. I read about the loopback modes in UG196 and found that the DRP's need to be modified in order to enable the internal loopback. The chapter on loopback mentions that the drp address 26[6:3] nee... 24 Jun 2008 13:20

Linked Group for FPGAs & CPLDs
Hi, There is a new FPGA Linked in Group. Joining will allow you to find and contact other FPGA, CPLD members on LinkedIn. The goal of this group is to help members: -> Reach other members of FPGA & CPLD community -> Accelerate careers/business through referrals from FPGA Group members -> Know more than a n... 24 Jun 2008 12:18

Xilinx and RAM/ROM monitoring
Hi, I was wondering if a tool exists to monitor the content of a RAM, ROM connected to a Xilinx FPGA. I would like to be able to control the content of those memories like a debugging tool for microcontroller for example. Does anybody know if this type of "debug" option is available for FPGA developpment ? ... 27 Jun 2008 14:12

Xilinx SecureIP simulation and third-party simulators?
Starting with ISE 10.1, has begun migrating some hard-IP simulation models from Smartmodel to "SecureIP." For now, the SecureIP blocks can only be simulated in 1 simulator: Modelsim 6.3c (or later) " AR #30975 - 10.1 SecureIP libraries - Does NCSIM and VCS support Secure IP flow?" http://www.xilinx.com/support... 27 Jun 2008 20:22

DC-Fifo with write pointer confirm/clear
Hi, I have designed a VHDL single clock FIFO with write pointer that can either be confirmed or cleared that is the read side of the fifo does see the write counters only when these have been confirmed by the write side. One application can be the confirmation of a packet including a checksum at the end. If the... 24 Jun 2008 06:09

FPGA based database searching
Hello, I've been searching the internet for days now and still I'm not sure about what I am trying to do. Okay now, I've got a software implementation in ANSI-C for a complex database searching. The database is a proprietary format where I am saving data, which has to be given as a result, depending on t... 30 Jun 2008 07:34

Calls for Papers Reminder: International Conference on Communications Systems and Technologies (ICCST 2008)
Calls for Papers Reminder: International Conference on Communications Systems and Technologies (ICCST 2008) From: International Association of Engineers (IAENG) San Francisco, USA, 22-24 October, 2008 http://www.iaeng.org/WCECS2008/ICCST2008.html The conference ICCST'08 is held under the World Congress on Engin... 23 Jun 2008 08:36

Cellular automata on a S3E SK
Hi group, Another video by me to showcase another application I made. Just to show can be done with a Spartan 3E Starter Kit, creativity and some free time. Don't be afraid to ask for code ;) Enjoy! http://vimeo.com/1206340 (more info on the other side of the link) Regards, -Sergio ... 23 Jun 2008 01:28

is lwIP absolutely necessary for tcp-ip?
hello. i am trying to set up ethernet interface between my pc and a XUP Virtex2Pro board, and want to use tcp/ip. xilinx edk seems to have the lwip stack as a library. is it necessary to use this library, or can one still implement tcp/ip by suitably changing the ethertype/length field in the frame? in my case,... 24 Jun 2008 07:10