FPGA
in [Hardware]
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Xilinx register inits Hi, I have a problem with getting the correct startup values for an array of bytes on a Xilinx V5 When the array is declared it is initialised using a function (which of course has only constant inputs). In simulation the array appears to be correctly initialised, but when the bitfile is downloaded it looks as ... 27 Jun 2008 14:12
Hardware Demonstration Platform Hi all, Im working on trimode Ethernet Mac core on Virtex 4. There is a tool in thie core called ":Xilinx Hardware Demonstration Platform" which acually displays the peckects being send and you can also set some parameter for the packet like destination address, length etc. Now the problem is with the destination ... 26 Jun 2008 02:17
FPGA area use by module? On Jun 25, 3:01 pm, Philip Herzog <p...(a)arcor.de> wrote: Hi! I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since it was too full. Now I have to optimize or reduce some modules to win some area, but I can only guess which ones use a lot of ... 26 Jun 2008 10:29
RAM and shift register constraints On Jun 25, 4:44 pm, austin <aus...(a)xilinx.com> wrote: fmostafa, Which family? In V5, we have an added bit in the bitstream which prevents LUTRAM and SRL16/32 from being readback. The function performed is called GLUTMASK (not that it matters what it is called). It was added just so you do not ... 25 Jun 2008 12:56
RAM and shift register constraints hi all; I am using HWICAP to configure certain LUTs , and as mentioned in the HWICAP data sheet that "when LUTs are configured in Shift Register Mode or as a RAM. If a LUT is modified or just read back in a column that also has a LUT RAM or LUT shift register, then the LUT or shift register will be interrupted ... 25 Jun 2008 11:54
Xilinx tools in Windows or Linux - Suggestions Friends, I have been using the Xilinx tools ISE, EDK in Windows environment. But now planning to use Linux PC for running ISE and EDK. I am curious, which platform (Windows or Linux) is good for Xilinx tools? I am planning to use the ISE and EDK in GUI mode, not command line mode. Linux version would be Red h... 15 Jul 2008 08:10
Signal forwarding between FPGAs Hello Very easy question, but I just wanna make sure that I have done it the correct way so that I dont have to look in this simple stuff for errors :) Basically I have two FPGAs (Control & Target FPGAs) and I wanna foward data between them for receiving and sending single bits. My VHDL code for the Control... 29 Jun 2008 18:17
interfacing lcd to spartan3a dsp 1800 We are students who are trying to interface JHD1629a LCD to spartan 3a dsp 1800 board. In the board the are two slots of EXP connectors. We are confused how to join connect LCD with EXP connector slots. ... 25 Jun 2008 08:48
Beginner : Rotary switch (quad sw) Spartan 3E starter kit: I tried (like all beginners) to read rotary switch (knob) using FSM with 8 states, 4 for CW and 4 for CCW movements. I did not debounce phased switch inputs. It works fine. But I remember seeing much debate on this issue and claims of success with 4 FF's (plus debouncers). My design created... 27 Jun 2008 04:58
Writing to memory shared with System Generator Hi. I'm trying to write a couple of values to a block of memory that is read by the system generator during hw-co-sim. I Use a Sysgen shared memory block in my design. I write to the shared mem. using the following code. uint32_t *test; test = (uint32_t *)0x84018000; //Base address of shared mem. ... 25 Jun 2008 06:46 |