FPGA

EDK question
Hi everybody, I am using PPC to configure number of LUTs using HWICAP, my question is , Is it possible to generate an interrupt internally according to a change in register value , as i want to do new configuration depending on this value? thanks Fatma ... 2 Jul 2008 21:10

lwip for FPGA
Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microblaze microprocessor on a Xilinx FPGA board and vice versa as fast as possible. i dun need any error correction or the overheads like full TCP/IP. I am currently readin this article to unders... 8 Jul 2008 05:55

FIR filter with integer coefficients
Hai, Can i implement FIR filter in FPGA using fixed point number.. I referred various FIR filter implementation in FPGA all have used integer coefficients for their implementation and i am interested to know the difficulties of using fixed point numbers.I knew fixed point numbers utilize more hardware. I un... 30 Jun 2008 17:53

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Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)
I created a simple Verilog-2001 test-module: `default_nettype none module top #( parameter integer D_W = 16 ) ( input wire sel, input wire signed [D_W-1:0] ina, inb, output wire signed [D_W:0] out ); assign out = sel ? (ina - inb ) : (ina + inb); endmodule // : top `default_nettype wire ... 1 Jul 2008 01:03

ANNOUNCE: TimingAnalyzer version beta 0.85
Hello All, A new version beta 0.85 is now available. The following changes and additions have occurred. 1 Quickly add previously used Delays and Constraints from pop-up menu 2 The current state is inverted automatically when adding new pulse if the newstate in the toolbar is the same as the current state ... 5 Jul 2008 22:43

arithmetic problem
Hi, the following code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; .... rnext.addr <= std_logic_vector(unsigned(rreg.addr) + 1); .... yields the following error : Line 140. Expression in type conversion to std_logic_vector has 3 possible definitions in this scope, for example, U... 30 Jun 2008 14:47

EDK DMA peripherals?
Hi, I am using an EDK-generated PPC subsystem on a ML403. I wonder if it would be complicated to create a peripheral that has high speed master access to the SDRAM. I would like to build a shared memory frame buffer. Or are there any other good ways to achieve my goal? I don't want to use the onboard SRAM. ... 30 Jun 2008 07:34

Missing the simplest things - Active HDL - Beginners Questions
Guys.. I am *brand new* to Aldec Active HDL. What few cpld/pals that I have done have been with CUPL. I've started using ActiveHDL(Student Ver), writing some easy VHDL just to get acquainted with both VHDL and the Aldec tool. What I don't understand is the integrated implementation portion. If I were to wan... 30 Jun 2008 12:43

Still a Beginner: Accumulator has no reset
Xilinx ISE 9.2 and ISE 10.1 I wanted to design a simple correlator which correlates a 15 bit sequence with another sequence of 15 bytes (8 bit signed values = Sample below). I needed to zero the summation result after 15 samples, so I did. But compiler didn't. There is no warning but even the simulator does not se... 28 Jun 2008 18:49