FPGA

How do I program an fpga once it has been designed and layout is complete
Trying to design an FPGA from scratch, but not sure how this fpga should be programmed. It is going to be a tile concept fpga with a LUT SRAM architecture. I have the resources to write VHDL/Verilog, netlist it and do the layout(incl. routing), but how do I program this fpga? I guess this is something I am not t... 2 Jul 2008 01:39

Nintendo DS Screenshots / Video Capture
Hi All, I'm starting to look at building something that will allow me to take screenshots and do video capture of both of the Nintendo DS screens. Amazingly there is actually nothing available that you can buy to do this (publically anyway), so why not build it! I knew I was onto something when I found this.... 19 Jul 2008 01:44

Board for Hardware in loop
I am looking for fpga-dsp-board with USB Interface for hardware-in- loop. I don't think I want to mess with USB. I just want to use some easy to use board which will allow me to transfer data (at high speed) to-fro the board using simple instructions. Any recommendations? ... 1 Jul 2008 17:28

VHDL libraries
I am working with a processor core that is written in VHDL and relies on a BUNCH of IP vendor provided libraries. I was able to build all the required libraries in ActiveHDL and compile the top-level unit. When I went to implement the design in ISE, ActiveHDL didn't transfer over the library files. Hence, bo... 1 Jul 2008 19:32

Type Casting in verilog
I just wanted to know whether type casting in verilog is sythesizable or not? ... 1 Jul 2008 16:27

chipscope analyzer error
Hi there, I have the same problem, I find this document that say to start the server cs_server.sh before start the analyser http://www.xilinx.com/publications/xcellonline/xcell_55/xc_chipscope55.htm bye Oscar. On 13 Giu, 07:38, Alan Nishioka <a...(a)nishioka.com> wrote: On Jun 12, 9:25 am, "Symon" <symon_... 1 Jul 2008 06:10

Translate problem
when i try to translate it, it tells me this ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) 'DCM_SP_INST' in the design. To suppress this error specify the correct instance name or remove the constraint. my top.vhd, make use of a component from clockmanager.vhd ...inside clo... 3 Jul 2008 03:17

Design of a BFSK transmitter/receiver using Xilinx System Generator
I would like someone to comment my BFSK design as I am a student and not much experienced. ... 30 Jun 2008 23:01

What is TIEOFF_X0Y31
Hi, I ran into a problem which is related to TIEOFF_X0Y31. I opened FPGA_Editor and see such sites around Xilinx Virtex5. i am wondering what's this site for? I googled and could not get any infos. Thank you, Adam ... 3 Jul 2008 14:34

on FRAME_ECC_VIRTEX4 functionality
Hi all, I have two questions: 1.- On the meaning of the syndrome word: Virtex-4 Libraries Guide for HDL Designs says that syndrome(11) = 0 means there is a one bit error and that syndrome(10 downto 0) indicates the error position (pag 94). However, Virtex 4 FPGA Configuration User Guide (pag 75, latest version, a... 1 Jul 2008 11:17