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From: GSB on 9 Nov 2005 16:10 The match filter I implemented does an Integrate and Dump. Some Integrate and Dumps have the restriction that it perform the calculations on the entire symbol size and that it starts the Integrate at the start of the symbol. This method requires that the symbol size and start of the bit transitions be known before the Integrate and Dump can be correctly applied. However, the version of Integrate and Dump I implemented does not require the calculations to start at the bit transitions and can start from any position. In fact, my version increments by only 1 sample at a time. The output is not bits but transitions. This is done using both a sin and cos reference signal where each is multiplied with the RF signal, squared, and then both are summed. If you have four RF frequencies in the FSK modulation, then 4 sets of these calculations are needed where the maximum value denotes the strongest RF signal. This procedure does have the restriction that the Integrate and Dump be performed over the enire symbol size. The FSK signal I am trying to decode will change baud speed so a fixed symbol size cannot be used. Alternating 1 and 0's are used to derive the baud speed. Therefore, the problem I am facing is to detect the baud speed and then adjust the symbol size. One method to detect the symbol size is to Integrate and Dump on the smallest possible symbol size which is probably 300 bauds. Once the current baud speed is found, a second Integrate and Dump (I & D) will adjust its symbol size and decode the signals. However, if the first I & D will detect a 1200 baud speed by using a symbol size of 300 bauds, then this will create some errors since the entire symbol size is not being used for the I & D. Does anyone have a better or different method in detecting the symbol size?
From: Bevan Weiss on 9 Nov 2005 16:23
GSB wrote: > The match filter I implemented does an Integrate and Dump. Some > Integrate and Dumps have the restriction that it perform the > calculations on the entire symbol size and that it starts the Integrate > at the start of the symbol. This method requires that the symbol size > and start of the bit transitions be known before the Integrate and Dump > can be correctly applied. However, the version of Integrate and Dump I > implemented does not require the calculations to start at the bit > transitions and can start from any position. In fact, my version > increments by only 1 sample at a time. The output is not bits but > transitions. This is done using both a sin and cos reference signal > where each is multiplied with the RF signal, squared, and then both are > summed. If you have four RF frequencies in the FSK modulation, then 4 > sets of these calculations are needed where the maximum value denotes > the strongest RF signal. This procedure does have the restriction that > the Integrate and Dump be performed over the enire symbol size. The > FSK signal I am trying to decode will change baud speed so a fixed > symbol size cannot be used. Alternating 1 and 0's are used to derive > the baud speed. Therefore, the problem I am facing is to detect the > baud speed and then adjust the symbol size. > > One method to detect the symbol size is to Integrate and Dump on the > smallest possible symbol size which is probably 300 bauds. Once the > current baud speed is found, a second Integrate and Dump (I & D) will > adjust its symbol size and decode the signals. However, if the first > I & D will detect a 1200 baud speed by using a symbol size of 300 > bauds, then this will create some errors since the entire symbol size > is not being used for the I & D. > > Does anyone have a better or different method in detecting the symbol > size? From this I assume that you are using some kind of encoding such as manchester encoding on the transmitted bits. You must have some bit timing information to properly extract the bits, so you need to transmit this as well as the actual bit information. If you're using manchester encoding then you still perform matched filtering, and could still use the integrate and dump method over half the bit width, where the timing information can be obtained using a PLL to sync to the bit transitions then multiply this by 2 to get the 'half bit' periods. I can't think of any clean way of doing this if using 4-FSK, unless you have two sets of orthogonal 2-FSK each with manchester encoding on the bitstream and then just multiplex them together at the receiving end. I also haven't had much experience with different variants of FSK so could be totally wrong bout the possibilities. |