Prev: Xilinx DDR2 Interface
Next: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
From: Moazzam on 25 Apr 2008 01:15
On Apr 24, 11:17 pm, Kevin Neilson
<kevin_neil...(a)removethiscomcast.net> wrote:
> Moazzam wrote:
> > On Apr 21, 10:12 pm, Kevin Neilson
> > <kevin_neil...(a)removethiscomcast.net> wrote:
> >> Haile Yu (Harry) wrote:
> >>> Dear all,
> >>> I've designed a macro, and put "ring.nmc" file in my project dir.
> >>> In my verilog module file, I wrote
> >>> ...
> >>> ring r1(.en(en),.ro(ro));
> >>> ...
> >>> to instantiate ring macro, but failed.
> >>> Any one could give some hint?
> >>> Thank you!
> >> If this is a ring oscillator, you may be having problems with the tools
> >> stripping away the logic.  -Kevin
>
> > Hi,
> > Kevin is right, also I use macros: declared as black box and write
> > their "portlist followed by endmodule " in a "macro_name.v" file in
> > the working directory.
>
> > Hope this helps,
> > /MH
>
> I'm not sure what you mean, and your syntax is unusual:  I think a
> "macro" is a software term.  Anyway, I'm not sure what the issue is
> here, but if you are trying to make a ring oscillator, one problem is
> that the synthesizer and mapper try to strip it away because it's a
> combinatorial loop and makes no sense from a logical standpoint.  So you
> might have to put some sort of "keep" directives to prevent this.  -Kevin- Hide quoted text -
>
> - Show quoted text -


Hi,
I will try to explain my previous post:

while making an instance of a macro file, as described by OP,I use
following syntax:

//-----------------------------------------------------------------//
ring r1(.en(en),.ro(ro)); //synthesis black_box

Make a new file in editor as:

module ring (
en,
ro
);

input enable;
output ro;

endmodule

//------------------------------------------------------------//

In my knowledge, making a file as above avoids synthesis error of
unavailability of file.
And declaration of instance as a blackbox would make the tool search
for a netlist of
the macro.

I may not be following the exact steps but it actually works for me
while playing with
Bus Macros of Dynamic Partial reconfiguration or working with EDN/NGC
files with no
verilog RTL.

/MH



First  |  Prev  | 
Pages: 1 2
Prev: Xilinx DDR2 Interface
Next: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff