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From: gretzteam on 31 May 2010 16:37
>Not incorrect -- just in need of clarification.
>The "DDS" style of NCO works well (and is by far what people usually
>mean when they say "NCO"), but gains a lot from the sine lookup -- this
>smooths out the inherent 'jagginess' from it's input clock, and
>essentially lets it interpolate zero crossing points in an analog system.
>When you just use the overflow then you have an unavoidable timing
>jitter that usually approaches +/- 1/2 an input clock peak-peak, with an
>RMS timing jitter that comes directly from the fact that the timing
>error is a sawtooth wave -- if you can stand this in your application,
>then you're home free.
I see. I was expecting the peak-to-peak jitter would be 1 input clock peak
to peak. I don't think there is a way around this if I'm only willing to
use 'nice-synthesizable rising-edge only digital logic'. However, if the
input clock is fast relative to the generated clock, and the NCO has a good
resolution, the RMS jitter can be made quite low.
From: gretzteam on 31 May 2010 16:42
>Form a reference clock signal that is jitter free and of the same
>exact frequency and same average phase as the NCO. The RMS value of
>the time diffeence of the NCO clock edges relative to the reference
>clock, divided by the period, is the RMS jitter as a dimensionless
>(If you don't divide it by the period, it's the RMS jitter in
>For a given NCO you might be able to compute this analytically
>from parameters such as your N and M, if it is important to
This is where I'm struggling. You'd need to calculate the error term for at
least on whole period of the NCO (by period I mean the '6 6 6 6 7' in the
How can you go from M and N, and calculate a sequence such as '6 6 6 6 7',
apart from running the simulation? It's easy enough to write the 'for loop'
but I wonder if there is a quicker/nicer way.
From: Steve Pope on 31 May 2010 16:50
In article <D5-dnVlh-YzagpnRnZ2dnUVZ_hOdnZ2d(a)giganews.com>,
gretzteam <gretzteam(a)n_o_s_p_a_m.yahoo.com> wrote:
>>Form a reference clock signal that is jitter free and of the same
>>exact frequency and same average phase as the NCO. The RMS value of
>>the time diffeence of the NCO clock edges relative to the reference
>>clock, divided by the period, is the RMS jitter as a dimensionless
>This is where I'm struggling. You'd need to calculate the error term for at
>least on whole period of the NCO (by period I mean the '6 6 6 6 7' in the
>How can you go from M and N, and calculate a sequence such as '6 6 6 6 7',
>apart from running the simulation?
Nothing wrong with running a sim if an analytical expression does
not come immediately to mind.
Back to the modulo arithmetic.
Fc = system clock
MOD = modulo of the MSB's of the phase counter
NLSB = number of LSB bits (counting in binary) in the phase counter
to the right of the above MSB's
Your NCO can then generate any frequency which is a multiple of
Fc / (MOD * 2^NLSB)
without any intrinsic jitter. If that is good enough for your
application then do it, and save yourself the trouble of calculating
the jitter in a suboptimal design.
From: dbd on 31 May 2010 17:26
On May 31, 12:08 pm, Eric Jacobsen <eric.jacob...(a)ieee.org> wrote:
> The OP's description of an NCO seems strange, though, and I'm trying to
> get clarification to better understand the issue. Usually fout is a
> function of the PIR contents and the update frequency only. I'm not
> sure how his description of N and M fit, especially since those terms
> are typical for synthesizers, not NCOs.
> Eric Jacobsen
> Minister of Algorithms
> Abineau Communicationshttp://www.abineau.com
My guess is that the OP is talking "fractional-N synthesizer" and Tim
and Steve are talking "DDC".
My post was some fractional-N literature in case my suspicion is
Should we start a pool on it?
Dale B. Dalrymple
From: Steve Pope on 31 May 2010 17:53
dbd <dbd(a)ieee.org> wrote:
>My guess is that the OP is talking "fractional-N synthesizer" and Tim
>and Steve are talking "DDC".
OP clarified he/she is talking about just the NCO.