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From: aerosmith on 10 Dec 2006 11:48
Hi,

Could anyone give me some differences between MIPS and the ARM
architecture. I am not looking for very low (close to hardware) level
information but just to know which architecture has/lacks what features.

Thanks in advance.
From: jon@beniston.com on 11 Dec 2006 07:41

> Could anyone give me some differences between MIPS and the ARM
> architecture. I am not looking for very low (close to hardware) level
> information but just to know which architecture has/lacks what features.

Here's a few little things:

More GPR in MIPS. Special purpose multiply registers in MIPS. Register
banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
for one operand in ARM.

Cheers,
Jon

From: Paul A. Clayton on 11 Dec 2006 09:29
jon(a)beniston.com wrote:
[snip]
> More GPR in MIPS. Special purpose multiply registers in MIPS. Register
> banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
> for one operand in ARM.

Don't MIPS' Shadow Register Sets act similar to ARM's banked registers
(i.e., providing some registers for interrupt contexts--except with
MIPS it is
a full set of 31 GPRs)?

Also I don't think ARM has a branch/jump delay slot, correct?
ARM also has a load/store multiple registers instruction, correct?
ARM defines the Program Counter as a GPR.
I don't think ARM reserves a hard-wired-to-zero register (as MIPS
certainly does).


Paul A. Clayton
one who never really looked at the ARM ARM
but who has a minimal familiarity with MIPS

From: =?iso-8859-1?q?Torben_=C6gidius_Mogensen?= on 11 Dec 2006 10:25
"Paul A. Clayton" <paaronclayton(a)earthlink.net> writes:

> jon(a)beniston.com wrote:
> [snip]
>> More GPR in MIPS. Special purpose multiply registers in MIPS. Register
>> banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
>> for one operand in ARM.

Why stupid?

> Also I don't think ARM has a branch/jump delay slot, correct?

Correct.

> ARM also has a load/store multiple registers instruction, correct?

Correct.

> ARM defines the Program Counter as a GPR.

Correct.

> I don't think ARM reserves a hard-wired-to-zero register (as MIPS
> certainly does).

Correct.

Also:

- ARM has condition flags (x86-style) where MIPS has branch-equal /
branch-not-equal instructions and for more complex comparisons
needs to set condition codes in GPRs (using set-less-than, etc.)
and test these by BEQ/BNE.

- ARM has auto-increment/decrement on load/store instructions and can
scale register-based offsets.

- ARM has a carry flag that makes multi-word integers easy to handle.

Torben
From: Tim McCaffrey on 11 Dec 2006 13:58
In article <hTWeh.53235$rv4.7765(a)edtnps90>, aerosmith(a)pandoras.box says...
>
>Hi,
>
>Could anyone give me some differences between MIPS and the ARM
>architecture. I am not looking for very low (close to hardware) level
>information but just to know which architecture has/lacks what features.
>
>Thanks in advance.

Interrupt handling, address modes, PSW (or not), # GPRs, floating point, size
of GPRs, where IP is located (one of GPRs or not), how long constants are
loaded.

The biggest difference between the two, from a higher level, is probably
floating point and addressing size: MIPS64 implementations usually
have floating point, and can address > 4G easily. ARM's support for FP is
limited, and usually not included, and it is a 32 bit architecture.

From an embedded point of view, the other difference might be that you don't
have to turn paging on with the MIPS to enable the cache.

- Tim

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