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From: Nick Maclaren on 3 Apr 2008 13:31

In article <6da0e4eb-7236-45a4-8582-acbd03385a71(a)u69g2000hse.googlegroups.com>,
David Kanter <dkanter(a)gmail.com> writes:
|> On Apr 3, 12:42 am, Terje Mathisen <terje.mathi...(a)hda.hydro.com>
|> wrote:
|>
|> It seems obvious to me that NTP relies on low level software and it's
|> reasonable to believe that SMT might make life more difficult.
|> However, a PLL is as far as I can tell (looking at wikipedia) an
|> analog or mixed signal device used to generate a frequency from a
|> reference clock. Perhaps what Nick means is a software implementation
|> of equivalent functionality...

!!! You are relying on WIKIPEDIA for your information? That might
well explain why you keep flaming me every time I post something
technically beyond the contents of Wikipedia :-(

The term predates stored-memory computers by decades, and it can be
used both in the above specific sense and its more general sense of
a particular type of feedback-controlled synchronisation mechanism.
You will find it in 1920s electrical engineering texts, for a start.


Regards,
Nick Maclaren.
From: Terje Mathisen on 3 Apr 2008 14:42
David Kanter wrote:
>> Nick wrote the SNTP (Simple NTP) fallback code which is part of the
>> official open source NTP implementation, and yes, high-performance NTP
>> does require predictable interrupt latencies and either a core-locked
>> ntp deamon or a globally synchronized sub-microsecond clock.
>
> That's fair enough.
>
> However, given Nick's record both within this thread and in other
> threads, I have a hard time trusting anything he says as reliable
> information.
>
> It seems obvious to me that NTP relies on low level software and it's
> reasonable to believe that SMT might make life more difficult.
> However, a PLL is as far as I can tell (looking at wikipedia) an
> analog or mixed signal device used to generate a frequency from a
> reference clock. Perhaps what Nick means is a software implementation
> of equivalent functionality...

NTP is in fact a nano-second level sw hybrid PLL/FLL loop, with adaptive
Q value, capable of capturing and according to at least one measure,
optimally steer the clock to match a "true reference"

>
> The PLLs in modern chips are unaffected by SMT and are probably not
> software visible (i.e. if your chip is magically generates the
> required clock signal, the SW could probably never know the
> diference).

NTP and HW PLL is not related. (Well, except for modern attempts to move
the protocol directly onto the Ethernet hw).

Terje

>
> DK


--
- <Terje.Mathisen(a)hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"
From: David Kanter on 3 Apr 2008 23:50
On Apr 3, 10:31 am, n...(a)cus.cam.ac.uk (Nick Maclaren) wrote:
> In article <6da0e4eb-7236-45a4-8582-acbd03385...(a)u69g2000hse.googlegroups.com>,David Kanter <dkan...(a)gmail.com> writes:
>
> |> On Apr 3, 12:42 am, Terje Mathisen <terje.mathi...(a)hda.hydro.com>|> wrote:
>
> |>
> |> It seems obvious to me that NTP relies on low level software and it's
> |> reasonable to believe that SMT might make life more difficult.
> |> However, a PLL is as far as I can tell (looking at wikipedia) an
> |> analog or mixed signal device used to generate a frequency from a
> |> reference clock. Perhaps what Nick means is a software implementation
> |> of equivalent functionality...
>
> !!! You are relying on WIKIPEDIA for your information? That might
> well explain why you keep flaming me every time I post something
> technically beyond the contents of Wikipedia :-(

No Nick, I correct you because you are wrong. Tera is not SoEMT,
SoEMT in a scalar CPU is equivalent to SMT, etc. etc.

> The term predates stored-memory computers by decades, and it can > be
> used both in the above specific sense and its more general sense of
> a particular type of feedback-controlled synchronisation mechanism.
> You will find it in 1920s electrical engineering texts, for a start.

Wonderful.

DK
From: Nick Maclaren on 4 Apr 2008 04:24

In article <79574aae-c6d9-4fcb-b37c-4e3540a4e6d9(a)2g2000hsn.googlegroups.com>,
David Kanter <dkanter(a)gmail.com> writes:
|>
|> No Nick, I correct you because you are wrong. Tera is not SoEMT,
|> SoEMT in a scalar CPU is equivalent to SMT, etc. etc.

Sigh. Let us assume that you are right there - it is quite impossible
to deduce precisely how other people use such terms, in the complete
absence of definitions. And, no, vague descriptions, don't count.
At one stage, many people were calling the Tera SoEMT :-(

====>> But that is and always was irrelevant to my point. <<====

To consider your claim above "SoEMT in a scalar CPU is equivalent to
SMT" and to repeat a variation of a previous point:

Many mainframes (IBM 370s among them) had several hardware contexts,
and switched between them on certain classes of event. Were THEY
also SMT? If not, WHY not?


Regards,
Nick Maclaren.
From: David Kanter on 4 Apr 2008 15:02
On Apr 4, 1:24 am, n...(a)cus.cam.ac.uk (Nick Maclaren) wrote:
> In article <79574aae-c6d9-4fcb-b37c-4e3540a4e...(a)2g2000hsn.googlegroups.com>,David Kanter <dkan...(a)gmail.com> writes:
>
> |>
> |> No Nick, I correct you because you are wrong. Tera is not SoEMT,
> |> SoEMT in a scalar CPU is equivalent to SMT, etc. etc.
>
> Sigh. Let us assume that you are right there - it is quite impossible
> to deduce precisely how other people use such terms, in the complete
> absence of definitions. And, no, vague descriptions, don't count.
> At one stage, many people were calling the Tera SoEMT :-(

Nick - I provided you a link to a paper that very clearly articulated
why SMT and SOEMT on a scalar (or single issue for the terminology
impaired) CPU are the same.

> ====>> But that is and always was irrelevant to my point. <<====
>
> To consider your claim above "SoEMT in a scalar CPU is equivalent to
> SMT" and to repeat a variation of a previous point:

> Many mainframes (IBM 370s among them) had several hardware contexts,
> and switched between them on certain classes of event. Were THEY
> also SMT? If not, WHY not?

Nick, someone already explained that to you, to quote bill todd's
post:

"SoeMT is a mechanism that
supports multiple *hardware* thread contexts within a *single core*
aimed at keeping *that core* busy rather than idling it while a single
thread is waiting for a memory access. Thread-switch-on-page-miss is
a
mechanism that supports multiple *software* thread contexts within the
*operating system* aimed at keeping the *system* busy rather than
idling
it while a single thread is waiting for a disk access.

So while the two mechanisms are certainly *analogous*, they're hardly
both part of the SMT acronym (which AFAIK is clearly core-centric in
nature, particularly with respect to the 'simultaneous' aspect -
though
for SoeMT the 'simultaneity' is in having multiple contexts
core-resident and executable rather than in having them actually
execute
in parallel in a given clock possibly even within the same core
pipeline
stage as the most general SMT implementation would allow)."

Other than that I'm not familiar enough with the 370 to really
comment.

DK
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