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From: LC on 12 Apr 2008 05:59
Hi,

I'm trying to port some code from Xilinx to Altera
and I'm in a bit of a problem by not having UNISIM lib
on Altera.

I use only a few components from the unisim lib so may
not be a big effort to write a vhdl component for each
one of them, providing I know the details what they do
exactly.

Can someone help me with the details of the following
components:

SRL16E
MULT18x18
RAMB16_S18
RAMB16_S9
RAMB16_S4
RAMB16_S18_S18


Or maybe there is a clever way of doing this.

Help is appreciated.
Thanks.

Luis C.
From: Arlet Ottens on 12 Apr 2008 06:47
LC wrote:

> I'm trying to port some code from Xilinx to Altera
> and I'm in a bit of a problem by not having UNISIM lib
> on Altera.
>
> I use only a few components from the unisim lib so may
> not be a big effort to write a vhdl component for each
> one of them, providing I know the details what they do
> exactly.
>
> Can someone help me with the details of the following
> components:
>
> SRL16E
> MULT18x18
> RAMB16_S18
> RAMB16_S9
> RAMB16_S4
> RAMB16_S18_S18

This may be helpful:

http://toolbox.xilinx.com/docsan/xilinx82/books/docs/lib/lib.pdf
From: vladitx on 12 Apr 2008 09:51
On Apr 12, 12:59 pm, LC <cupidoREM...(a)mail.ua.pt> wrote:
>
> Can someone help me with the details of the following
> components:
>
> SRL16E

In Verilog-2001:

module SRL16E #(
parameter INIT=16'h0000
) (
output Q,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);

reg [15:0] r;

assign Q = r[{A3, A2, A1, A0}];

initial
r = INIT;

always @(posedge CLK)
if (CE)
r <= {r[14:0], D};

endmodule
From: LC on 14 Apr 2008 05:55
More than helpful, it has all of it.
Thanks.
lc

Arlet Ottens wrote:
>
> This may be helpful:
>
> http://toolbox.xilinx.com/docsan/xilinx82/books/docs/lib/lib.pdf
From: LC on 14 Apr 2008 06:24
Tks,
lc.

vladitx wrote:
> On Apr 12, 12:59 pm, LC <cupidoREM...(a)mail.ua.pt> wrote:
>> Can someone help me with the details of the following
>> components:
>>
>> SRL16E
>
> In Verilog-2001:
>
> module SRL16E #(
> parameter INIT=16'h0000
> ) (
> output Q,
> input A0,
> input A1,
> input A2,
> input A3,
> input CE,
> input CLK,
> input D
> );
>
> reg [15:0] r;
>
> assign Q = r[{A3, A2, A1, A0}];
>
> initial
> r = INIT;
>
> always @(posedge CLK)
> if (CE)
> r <= {r[14:0], D};
>
> endmodule
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