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From: jjlindula on 21 Apr 2008 19:34
Hello, I have a question about instantiating a module in a verilog
testbench. Sometimes the instantiation may have lots of inputs and
output that you may not want to appear in the ModelSim simulation, is
there a way to stimulate particular signals in a module so the
simulation won't include (display) all of the i/o in your design.
Below if my testbench:

//
// Copyright 2006 Mentor Graphics Corporation
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH
IS THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO
LICENSE TERMS.
//
`timescale 1ns/1ns


module test_counter;

reg clock_80mhz, fiber_rst;

reg delay_clock;

wire pin_in;




ModelSimTopblock dut ( fib_rx_dv,
fib_rx_er,
fib_rx_clk,
reset_fpga,
clock_80mhz,
fiber_rcv_rdreq,
fiber_go_xmit,
fiber_wrreq,
fiber_rst,
pin_in,
fib_rx_data,
fiber_tx_data,
//------------------------------
fib_tx_en,
fib_tx_er,
fifo_ef_dsp,
dsp_fib_rx_interrupt,
fib_rx_data_led,
fib_tlk_sig_loss,
fib_tx_data_led,
fifo_ef_ctl,
pin_out,
fib_tx_data,
fiber_data_rcvd
);

parameter tON = 15, tOFF = 7;


initial // Clock generator
begin
clock_80mhz = 0;
forever #15 clock_80mhz = !clock_80mhz;
end


always
begin
#tON delay_clock = 0;
#tOFF delay_clock = 1;
end


initial // Test stimulus
begin
fiber_rst = 1;
#5 fiber_rst = 1;
#4 fiber_rst = 0;
end

assign pin_in = delay_clock;


initial
$monitor($stime,, fiber_rst,, clock_80mhz,,, pin_out);

endmodule

When I launch modelsim all of the io signals of the ModelSimTopblock
would be present in the sim. Can I do something like this:



ModelSimTopblock dut ( 0,
fib_rx_er,
0,
0
clock_80mhz,
0,
0
fiber_wrreq,
fiber_rst,
pin_in,
fib_rx_data,
fiber_tx_data,
//------------------------------
0,
0,
0
0,
0,
0,
fib_tx_data_led,
fifo_ef_ctl,
pin_out,
fib_tx_data,
fiber_data_rcvd
);
Here only a few signals would be stimulated and few signals would
appear in the ModelSim simulation window. Is there a way to do this?

thanks,
joe
From: jjlindula on 21 Apr 2008 19:44
On Apr 21, 4:34 pm, "jjlind...(a)hotmail.com" <jjlind...(a)hotmail.com>
wrote:
> Hello, I have a question about instantiating a module in a verilog
> testbench. Sometimes the instantiation may have lots of inputs and
> output that you may not want to appear in the ModelSim simulation, is
> there a way to stimulate particular signals in a module so the
> simulation won't include (display) all of the i/o in your design.
> Below if my testbench:
>
> //
> // Copyright 2006 Mentor Graphics Corporation
> //
> // All Rights Reserved.
> //
> // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH
> IS THE PROPERTY OF
> // MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO
> LICENSE TERMS.
> //
> `timescale 1ns/1ns
>
> module test_counter;
>
> reg clock_80mhz, fiber_rst;
>
> reg delay_clock;
>
> wire pin_in;
>
> ModelSimTopblock dut ( fib_rx_dv,
> fib_rx_er,
> fib_rx_clk,
> reset_fpga,
> clock_80mhz,
> fiber_rcv_rdreq,
> fiber_go_xmit,
> fiber_wrreq,
> fiber_rst,
> pin_in,
> fib_rx_data,
> fiber_tx_data,
> //------------------------------
> fib_tx_en,
> fib_tx_er,
> fifo_ef_dsp,
> dsp_fib_rx_interrupt,
> fib_rx_data_led,
> fib_tlk_sig_loss,
> fib_tx_data_led,
> fifo_ef_ctl,
> pin_out,
> fib_tx_data,
> fiber_data_rcvd
> );
>
> parameter tON = 15, tOFF = 7;
>
> initial // Clock generator
> begin
> clock_80mhz = 0;
> forever #15 clock_80mhz = !clock_80mhz;
> end
>
> always
> begin
> #tON delay_clock = 0;
> #tOFF delay_clock = 1;
> end
>
> initial // Test stimulus
> begin
> fiber_rst = 1;
> #5 fiber_rst = 1;
> #4 fiber_rst = 0;
> end
>
> assign pin_in = delay_clock;
>
> initial
> $monitor($stime,, fiber_rst,, clock_80mhz,,, pin_out);
>
> endmodule
>
> When I launch modelsim all of the io signals of the ModelSimTopblock
> would be present in the sim. Can I do something like this:
>
> ModelSimTopblock dut ( 0,
> fib_rx_er,
> 0,
> 0
> clock_80mhz,
> 0,
> 0
> fiber_wrreq,
> fiber_rst,
> pin_in,
> fib_rx_data,
> fiber_tx_data,
> //------------------------------
> 0,
> 0,
> 0
> 0,
> 0,
> 0,
> fib_tx_data_led,
> fifo_ef_ctl,
> pin_out,
> fib_tx_data,
> fiber_data_rcvd
> );
> Here only a few signals would be stimulated and few signals would
> appear in the ModelSim simulation window. Is there a way to do this?
>
> thanks,
> joe

Hello again, I tried putting 0 in the instantiation and it gives an
error. There must be some way to create a testbench were only a few
signals are stated and thereby would create a simulation consisting of
only the signals of interest are displayed.
From: RCIngham on 22 Apr 2008 04:36
>On Apr 21, 4:34 pm, "jjlind...(a)hotmail.com" <jjlind...(a)hotmail.com>
>wrote:
>> Hello, I have a question about instantiating a module in a verilog
>> testbench. Sometimes the instantiation may have lots of inputs and
>> output that you may not want to appear in the ModelSim simulation, is
>> there a way to stimulate particular signals in a module so the
>> simulation won't include (display) all of the i/o in your design.

This is probably not the most appropriate forum for this question. Try
http://forums.mugweb.org/ instead.

From: HT-Lab on 22 Apr 2008 06:13

<jjlindula(a)hotmail.com> wrote in message
news:7c110d97-7eaa-440e-a661-225a0fd05de2(a)f36g2000hsa.googlegroups.com...

...snip

> );
> Here only a few signals would be stimulated and few signals would
> appear in the ModelSim simulation window. Is there a way to do this?

I probably don't understand you question but you can simply drag and drop
the signals of interest from the Objects window onto the Waveform window. If
you want to do this from a script than look up the "add wave" command in the
reference manual.

Hans.
www.ht-lab.com


>
> thanks,
> joe


From: jjlindula on 22 Apr 2008 10:40
On Apr 22, 2:13 am, "HT-Lab" <han...(a)ht-lab.com> wrote:
> <jjlind...(a)hotmail.com> wrote in message
>
> news:7c110d97-7eaa-440e-a661-225a0fd05de2(a)f36g2000hsa.googlegroups.com...
>
> ..snip
>
> > );
> > Here only a few signals would be stimulated and few signals would
> > appear in the ModelSim simulation window. Is there a way to do this?
>
> I probably don't understand you question but you can simply drag and drop
> the signals of interest from the Objects window onto the Waveform window. If
> you want to do this from a script than look up the "add wave" command in the
> reference manual.
>
> Hans.www.ht-lab.com
>
>
>
> > thanks,
> > joe

Hello, thanks for responding to my post. Sorry for me confusing
everyone. Let's say I have a large design that has lots of inputs and
outputs and let's say I'm only interested in a simulation consisting
of only a few inputs and outputs. When I run ModelSim it will add in
all the inputs/output of the module I am simulating, thus adding in
all of the inputs and outputs of my design into the waveform window. I
was hoping I could configure something so when the simulation finishes
it would display the signals I'm interested in. Is that possible? I'll
also try the other newsgroup and see if anyone has a solution.

thanks,
joe
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