Out-of-order (Dynamic pipeline) question?
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From: Davy on 17 Jan 2007 21:50 Hi all, I am new to CPU design and reading "Computer Organization and Design 2nd". There is a litter information about Out-of-order (Dynamic pipeline). And I found the MIPS design example is static pipeline. Hence, is there any good tutorial or article talk about how to design a simple Out-of-order (Dynamic pipeline) CPU? That I want to turn the MIPS design to Out-of-order one, is it feasible just for lab work :-), Thanks! Best regards, Davy
From: Finn Schiermer Andersen on 18 Jan 2007 05:12 "Davy" <zhushenli(a)gmail.com> writes: >Hi all, >I am new to CPU design and reading "Computer Organization and Design >2nd". There is a litter information about Out-of-order (Dynamic >pipeline). And I found the MIPS design example is static pipeline. >Hence, is there any good tutorial or article talk about how to design a >simple Out-of-order (Dynamic pipeline) CPU? That I want to turn the >MIPS design to Out-of-order one, is it feasible just for lab work :-), Depends on how much effort you are willing to spend. Expect it to be an order of magnitude harder than the pipeline in COD. If you want to experiment with out-of-order designs, have a look at the simplescalar tools (see http://www.simplescalar.com/). /Finn
From: Davy on 18 Jan 2007 19:20 Hi Finn, Thanks a lot for the information. I have read the SimpleScalar homepage. It said " in 2000 more than one third of all papers published in top computer architecture conferences used the SimpleScalar tools to evaluate their designs". Is it now remain popular in computer architecture research? Best regards, Shenli "Finn Schiermer Andersen дµÀ£º " > "Davy" <zhushenli(a)gmail.com> writes: > > >Hi all, > > >I am new to CPU design and reading "Computer Organization and Design > >2nd". There is a litter information about Out-of-order (Dynamic > >pipeline). And I found the MIPS design example is static pipeline. > > >Hence, is there any good tutorial or article talk about how to design a > >simple Out-of-order (Dynamic pipeline) CPU? That I want to turn the > >MIPS design to Out-of-order one, is it feasible just for lab work :-), > > Depends on how much effort you are willing to spend. Expect it > to be an order of magnitude harder than the pipeline in COD. > > If you want to experiment with out-of-order designs, have a look at the > simplescalar tools (see http://www.simplescalar.com/). > > /Finn
From: Finn Schiermer Andersen on 19 Jan 2007 03:57 "Davy" <zhushenli(a)gmail.com> writes: >Hi Finn, >Thanks a lot for the information. >I have read the SimpleScalar homepage. It said " in 2000 more than one >third of all papers published in top computer architecture conferences >used the SimpleScalar tools to evaluate their designs". Is it now >remain popular in computer architecture research? Note: I'm not a researcher, for me, it�'s justa hobby. The claims below may be a bit too strong. I think that the statement reflects that actual research into superscalars is a done deal. We know what we need to know about how to build them, their potential, and the cost of realizing that potential. Research has moved on. But a thorough understanding of superscalar design is still required to appreciate research in computer architecture. You might want to read about superscalar designs instead of (or in addition to) playing with tools. For specific designs look for articles on dec alpha axp 21264, mips r10000, ibm power4 or power5, intel pentium pro and intel Core. Long time ago when I started reading about superscalar design tradeoffs, I enjoyed "superscalar microprocessor design" by Mike Johnson (see http://en.wikipedia.org/w/index.php?title=Special:Booksources&isbn=0138756341 ). Enjoy the ride, /Finn >Best regards, >Shenli >"Finn Schiermer Andersen =D0=B4=B5=C0=A3=BA >" >> "Davy" <zhushenli(a)gmail.com> writes: >> >> >Hi all, >> >> >I am new to CPU design and reading "Computer Organization and Design >> >2nd". There is a litter information about Out-of-order (Dynamic >> >pipeline). And I found the MIPS design example is static pipeline. >> >> >Hence, is there any good tutorial or article talk about how to design a >> >simple Out-of-order (Dynamic pipeline) CPU? That I want to turn the >> >MIPS design to Out-of-order one, is it feasible just for lab work :-), >> >> Depends on how much effort you are willing to spend. Expect it >> to be an order of magnitude harder than the pipeline in COD. >> >> If you want to experiment with out-of-order designs, have a look at the >> simplescalar tools (see http://www.simplescalar.com/). >>=20 >> /Finn
From: Sandeep Dutta on 23 Jan 2007 09:47
Hi Davy > Hence, is there any good tutorial or article talk about how to design a > simple Out-of-order (Dynamic pipeline) CPU? That I want to turn the > MIPS design to Out-of-order one, is it feasible just for lab work :-), It maynot be as simple as that. In all probability you would need to reimplement the pipeline. I cannot offer you a tutorial, but you can see an example implementation of Out-of-order completion (in-order-issue) at http://www.niktech.com. The source code is in vhdl and is available for free. The out-of-order completion helps hide the latency for load/store , multiply & shift operations. Take a look at the module pipectrl.vhd this module detects hazards and asserts the stall signal. Hope that helps. Regards Sandeep |