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From: Tom Lyon on 1 Jul 2010 17:30
This patch allows IOMMU users to determine whether the hardware and software
support safe, isolated interrupt remapping. Not all Intel IOMMUs have the
hardware, and the software for AMD is not there yet.
Signed-off-by: Tom Lyon <pugs(a)cisco.com>
---

Version 2: previous ifdefs not needed.

MST has convinced me that any user level driver for PCI master devices can't
be safe unless there is an IOMMU protecting the APIC MSI/MSI-X interrupt
addresses from device writes. This interrupt remapping is not present in all
Intel IOMMUs and the code for the interrupt mapping in the AMD IOMMUs is not
implemented yet.

Needed by not-yet-accepted VFIO driver.

diff -uprN linux-2.6.34/drivers/pci/intel-iommu.c iommuapi-linux-2.6.34/drivers/pci/intel-iommu.c
--- linux-2.6.34/drivers/pci/intel-iommu.c 2010-05-16 14:17:36.000000000 -0700
+++ iommuapi-linux-2.6.34/drivers/pci/intel-iommu.c 2010-06-30 15:47:10.000000000 -0700
@@ -3705,6 +3705,10 @@ static int intel_iommu_domain_has_cap(st

if (cap == IOMMU_CAP_CACHE_COHERENCY)
return dmar_domain->iommu_snooping;
+ if (cap == IOMMU_CAP_SAFE_INTR_REMAP)
+ return intr_remapping_enabled;

return 0;
}
diff -uprN linux-2.6.34/include/linux/iommu.h iommuapi-linux-2.6.34/include/linux/iommu.h
--- linux-2.6.34/include/linux/iommu.h 2010-05-16 14:17:36.000000000 -0700
+++ iommuapi-linux-2.6.34/include/linux/iommu.h 2010-06-30 15:47:34.000000000 -0700
@@ -30,6 +30,7 @@ struct iommu_domain {
};

#define IOMMU_CAP_CACHE_COHERENCY 0x1
+#define IOMMU_CAP_SAFE_INTR_REMAP 0x2 /* isolates device intrs */

struct iommu_ops {
int (*domain_init)(struct iommu_domain *domain);
--
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