PEG Root Control and PEG Buffer Length
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From: forumposter32 on 30 Sep 2005 01:37 I found this: http://www.rojakpot.com/default.aspx?location=3&var1=130&var2=0 after seeing something called PEG Link Mode in my BIOS. Since I didn?t know what it was and why my X700 Pro gave me "failed VGA test" errors on startup, I decided to read about it. Anyway, does anybody know about PEG Root Control and PEG Buffer Length? I?m hoping disabling all three will result in me not having any stupid errors for nothing. -- Posted using the http://www.hardwareforumz.com interface, at author's request Articles individually checked for conformance to usenet standards Topic URL: http://www.hardwareforumz.com/ASUS-PEG-Root-Control-PEG-Buffer-Length-ftopict62867.html Visit Topic URL to contact author (reg. req'd). Report abuse: http://www.hardwareforumz.com/eform.php?p=316263
From: Paul on 30 Sep 2005 10:14 In article <7_316263_097f2054accefa50e2f0e166e5986b3a(a)hardwareforumz.com>, forumposter32 <UseLinkToEmail(a)HardwareForumz.com> wrote: > I found this: > http://www.rojakpot.com/default.aspx?location=3&var1=130&var2=0 > after seeing something called PEG Link Mode in my BIOS. Since I didn?t > know what it was and why my X700 Pro gave me "failed VGA test" > errors on startup, I decided to read about it. Anyway, does anybody > know about PEG Root Control and PEG Buffer Length? > > I?m hoping disabling all three will result in me not having any stupid > errors for nothing. PCI Express logic seems to be keyed to a 100MHz input clock. There is apparently limited room to overclock that clock, to accelerate the data rate on the PCI Express serial links. Since the transmission rate is rather high to begin with, there are definitely going to be physical limits as to how much overclock is possible. The thing is, the bandwidth on the x16 PCI Express slot is 4GB/sec in each direction. Say only 1GB/sec is being used. Speeding up the link to 4.4GB/sec isn't going to make much of a difference. PCI Express is a serial protocol. The data travelling on the serial interconnect is broken into packets. AFAIK, a packet can be up to 4KB in length. The PEG Buffer length presumably has something to do with making room for those packets of data. Reducing the buffer length might reduce the number of transactions in flight - maybe if some other part of the system is being starved for bandwidth, this would give you a way to tune the system ? I had hoped that by finding a datasheet for a PCI Express (client) device, there might be some more hints about how PCI Express works, but my one potential source for such a datasheet, placed no register info in their datasheet. Most companies cover datasheets under NDA and I would need a fancy business card to grease the wheels. (I had hoped that might shed some light on what Root Control is.) Paul
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