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From: robquigley on 15 Apr 2008 10:49
Hey everyone,

Im having difficulty with signals that i tie to zero or one (using
Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation.
They appear fine in pre synthesis simulation, as one or zero depending
on what i specify, but they always appear as z in post synthesis
simulation.

As a result of this i have pre and post synthesis simulation mismatch
results and also my bit file doesnt work properly on my fpga (Virtex
II).

I'm using XST in ISE 9.2.

Is there a way i can have XST take care of this or must i provide a
specific ground signal to a module if i wish to drive a constant zero
or one in a circuit? I've inherited some code with *lots* of zero's
and one's specified like this and it appeared to work ok in Leonardo
Spectrum (our previous synthesis tool).

Any help would be appreciated.


Cheers,



Rob.
From: John_H on 15 Apr 2008 11:38
robquig...(a)gmail.com wrote:
> Hey everyone,
>
> Im having difficulty with signals that i tie to zero or one (using
> Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation.
> They appear fine in pre synthesis simulation, as one or zero depending
> on what i specify, but they always appear as z in post synthesis
> simulation.
>
> As a result of this i have pre and post synthesis simulation mismatch
> results and also my bit file doesnt work properly on my fpga (Virtex
> II).
>
> I'm using XST in ISE 9.2.
>
> Is there a way i can have XST take care of this or must i provide a
> specific ground signal to a module if i wish to drive a constant zero
> or one in a circuit? I've inherited some code with *lots* of zero's
> and one's specified like this and it appeared to work ok in Leonardo
> Spectrum (our previous synthesis tool).
>
> Any help would be appreciated.
>
>
> Cheers,
>
>
>
> Rob.

The Verilog 1s and 0s should work fine. I'd suggest finding the
signals in your post-synthesis verilog file. You should find reason
for the signals not being strict 1s or 0s. Anything else here on this
newsgroup would be conjecture. Find the signals in the file and you
find a way to avoid the z.
From: Muzaffer Kal on 15 Apr 2008 12:49
On Tue, 15 Apr 2008 07:49:23 -0700 (PDT), robquigley(a)gmail.com wrote:

>Hey everyone,
>
>Im having difficulty with signals that i tie to zero or one (using
>Verilog 1'b0, 1'b1 etc) appearing as z's in post synthesis simulation.
>They appear fine in pre synthesis simulation, as one or zero depending
>on what i specify, but they always appear as z in post synthesis
>simulation.
>
Depending on how the optimization is done, it is possible that the
constants are propagated to where they are used to leave the original
nets unused/unconnected; this may be your problem.

>As a result of this i have pre and post synthesis simulation mismatch
>results and also my bit file doesnt work properly on my fpga (Virtex
>II).

This may not necessarily be the case. Before you blame the tool, look
at your check list and see if any check marks are missing? (you say
you don't have a check list, here is a sample: did you run STA?, do
you meet timing? did you constrain your multi-cycle paths correctly?
did you make sure all asynch paths are managed safely and all async
path flops are turned off for back-annotated simulations? I am sure
many can be added to this list)

Another item you can check is to look at the gate level and find a
node where any of your constant signals would be used. If you can find
a simple enough logic implementation you can verify for yourself that
the constant net is not needed in the logic and that the constant has
been already inserted into the logic before optimization.
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