Priority among T0 & T1
in [Embedded]
|
Prev: you see big things and more ************************************************ **********************
Next: lpc2378
From: CB_Rajesh on 3 Jul 2008 15:56 As among T0 & T1 , T0 has got higher priority than T1 , if both are called at the same time , T0 starts executing first . But internally how does the control go back to T1 . I tried this in Keil in the debug mode and found that the after RETI of T0 control goes to the main prog and then returns to T1. Can somebody put some more light on this ? Thanks in advance.
From: Francisco Rodriguez on 4 Jul 2008 07:14 Hi CB_Rajesh "CB_Rajesh" <cb.rajesh.in(a)gmail.com> escribi� en el mensaje news:g8Odnc5q5qFts_DVnZ2dnUVZ_vadnZ2d(a)giganews.com... > As among T0 & T1 , T0 has got higher priority than T1 , if both are called I assume you're talking about the 8051 microcontroller here. You're right if T0 and T1 have the same priority value, but remember you can alter an ISR priority with the interrupt priority register. > at the same time , T0 starts executing first . But internally how does the > control go back to T1 . I tried this in Keil in the debug mode and found > that the after RETI of T0 control goes to the main prog and then returns to > T1. Can somebody put some more light on this ? Thanks in advance. > > That's exactly what the manual says. The microcontroller does *not* service pending interrupts when executing the RETI instruction. This has been used in the past to create a "single-step" execution feature with a debugger/monitor installed as an ISR that does *not* clear the interrupt flag. When the ISR (the debugger) finishes (with a RETI instruction) the execution flow goes backs to the main program for a single instruction and then returns to the ISR again (remember the interrupt flag has not been cleared inside the ISR). This can only be used with interrupt flags that are *not* automatically cleared when the associated ISR is entered. Reading the manual, this applies to the serial port ISR only in the standard 8051 model. Best regards Paco ================================================================ Francisco Rodriguez Ballester (prodrig(a)disca.upv.es) Postal address: Dept. DISCA, ETS Informatica Aplicada, 1N-5 Universidad Politecnica de Valencia c/Camino de Vera s/n, E-46022, Valencia (Spain) tlf: +(34) 96 387 70 07 ext. 85704 - fax: +(34) 96 387 75 79 ================================================================
From: cb.rajesh.in on 28 Jul 2008 21:38
On Jul 4, 4:14 pm, "Francisco Rodriguez" <prod...(a)disca.upv.es> wrote: > Hi CB_Rajesh > > "CB_Rajesh" <cb.rajesh...(a)gmail.com> escribió en el mensajenews:g8Odnc5q5qFts_DVnZ2dnUVZ_vadnZ2d(a)giganews.com... > > > As among T0 & T1 , T0 has got higher priority than T1 , if both are called > > I assume you're talking about the 8051 microcontroller here. > You're right if T0 and T1 have the same priority value, > but remember you can alter an ISR priority with the interrupt priority register. > > > at the same time , T0 starts executing first . But internally how does the > > control go back to T1 . I tried this in Keil in the debug mode and found > > that the after RETI of T0 control goes to the main prog and then returns to > > T1. Can somebody put some more light on this ? Thanks in advance. > > That's exactly what the manual says. > > The microcontroller does *not* service pending interrupts when executing the RETI > instruction. > > This has been used in the past to create a "single-step" execution feature with a > debugger/monitor installed as an ISR that does *not* clear the interrupt flag. > When the ISR (the debugger) finishes (with a RETI instruction) the execution flow > goes backs to the main program for a single instruction and then returns > to the ISR again (remember the interrupt flag has not been cleared inside the ISR). > > This can only be used with interrupt flags that are *not* automatically cleared > when the associated ISR is entered. Reading the manual, this applies > to the serial port ISR only in the standard 8051 model. > > Best regards > Paco > ================================================================ > Francisco Rodriguez Ballester (prod...(a)disca.upv.es) > Postal address: Dept. DISCA, ETS Informatica Aplicada, 1N-5 > Universidad Politecnica de Valencia > c/Camino de Vera s/n, E-46022, Valencia (Spain) > tlf: +(34) 96 387 70 07 ext. 85704 - fax: +(34) 96 387 75 79 > ================================================================ Thanks all for your help .. The info had been really helpful ! ! ! |