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From: Sunny on 20 Feb 2006 03:18
Hi
I am writing synthesizable Verilog code for a DPRAM. It has two ports,
Port A and Port B.
For each port theres is a separate clock and separate clock_enable.
This is the code I wrote

reg [ 4: 0] read_addr_a;
reg [ 4: 0] read_addr_b;

always @ (posedge clock0)
if (clocken0)
begin
read_addr_a <= address_a;
read_addr_b <= address_b;
end

always @ (posedge clock1)
if (~clocken0 & clocken1)
begin
read_addr_a <= address_a;
read_addr_b <= address_b;
end

Can't resolve multiple constant drivers for net "read_addr_a[4] in the
begiing of the first posedge block.
Even though read_addr_a and read_addr_b are having multiple drivers
but they are in different clock domains and different clock enables are
being used.

How can I resolve this. I am using Leonardo Spectrum and Precision RTL.

TIA
Sunny

From: Hendra on 20 Feb 2006 08:26
What you have is two FF driving the same wire, which is not allowed and
not synthesizable. That has nothing to do with the clock. Eventhough
you have the same clock, it is still not synthesizable.

Hendra

From: "Sylvain Munaut <SomeOne@SomeDomain.com>" on 20 Feb 2006 08:38
You have to do all the operation in a signal process ...

like (VHDL sorry ...)

process (clka, clkb)
begin
if rising_edge(clka) then
if clken_a = '1' then
...
end if;
end if;
if rising_edge(clkb) then
if clken_b = '1' then
...
end if;
end if;
end if;

From: mk<kal* on 20 Feb 2006 14:18
On 20 Feb 2006 00:18:00 -0800, "Sunny" <shiladitya.biswas(a)gmail.com>
wrote:

>Hi
>I am writing synthesizable Verilog code for a DPRAM. It has two ports,
>Port A and Port B.
>For each port theres is a separate clock and separate clock_enable.
>This is the code I wrote
>
>reg [ 4: 0] read_addr_a;
> reg [ 4: 0] read_addr_b;
>
>always @ (posedge clock0)
> if (clocken0)
> begin
> read_addr_a <= address_a;
> read_addr_b <= address_b;
> end
>
> always @ (posedge clock1)
> if (~clocken0 & clocken1)
> begin
> read_addr_a <= address_a;
> read_addr_b <= address_b;
> end
>
>Can't resolve multiple constant drivers for net "read_addr_a[4] in the
>begiing of the first posedge block.
> Even though read_addr_a and read_addr_b are having multiple drivers
>but they are in different clock domains and different clock enables are
>being used.
>
>How can I resolve this. I am using Leonardo Spectrum and Precision RTL.
>
>TIA
>Sunny

The problem is that you're trying to write to both address registers
using both clocks. Think about the hardware and you'll realize that
this is not necessary. read_addr_a should be written by clock0 by
clken0 only and the similarly for read_addr_b, ie

always @ (posedge clock0)
if (clocken0)
begin
read_addr_a <= address_a;
end

always @ (posedge clock1)
if (clocken1)
begin
read_addr_b <= address_b;
end


Also as these are different clock domains you should never sample the
enable of side a with clock of side b without taking proper
precautions.

HTH.
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