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From: Jamie Lokier on 11 May 2010 06:20
Benjamin Herrenschmidt wrote:
> On the other hand, it could also be a busticated marvell SATA driver :-)

I've seen similar ext3 corruption errors with an IDE on a Sigma
Designs EM8620 with ARM core. It's completely unrelated :-) But the
fault was in the IDE driver doing cache flushes too late after
starting to set up DMA. To diagnose it, we luckily found a
reproducible test case, then sprinkled full cache flushes at various
places to narrow it down, and eventually found that one full cache
flush in the driver itself sorted it out, which told us where the
fault was. From there it was easy.

-- Jamie
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From: Jamie Lokier on 12 May 2010 18:30
Shilimkar, Santosh wrote:
> There was a memory write barrier missing before the DMA descriptors
> are handed over to DMA controller.

On that note, are the cache flush functions implicit memory barriers?

-- Jamie
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From: Jamie Lokier on 14 May 2010 13:50
Russell King - ARM Linux wrote:
> On Thu, May 13, 2010 at 08:47:11AM +1000, Benjamin Herrenschmidt wrote:
> > Now, in the case at hand, which is my ARM based NAS, I believe this
> > is non cache-coherent and thus uses cache flush ops. I don't know ARM
> > well enough but I would expect these to be implicit barriers. Russell ?
> > Nico ?
>
> ARMv5 doesn't have a weak memory ordering model, and doesn't have any
> memory barrier instructions.

It does have buffered writes, doesn't it? Are they always flushed by
the cache flush ops?

-- Jamie
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