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From: The Specialist on 5 May 2008 20:40
Hi Ryan, I wanted to try that once before as well.  I think it is a limitation of of only being able to run one bitfile at a time.  It would be cool though...wink wink.  I am not really sure how it would work though, since I believe most FPGA devices can only hadle one bitfile at a time.  If I were you this is what I would do.Start with a top-level VI like Mehak said.  Lay down your 2 subsystems like subVIs.  Then attach all the inputs and ouputs to each individual subsystem.  Then compile the VI.  I know it is kind of a cheap workaround, but you can still have you developers individually work on there own portions without effecting the opposite VI.  You can also let them both have their own DMA to get the information back to the host without interfering with each other.  Plus since everything on a FPGA runs in true hardware parallel your not eating up each others CPU or anything.  On the host side you will only have one FPGA reference, but then it splits so that two different parts of the of the FPGAs code are being used in two different parts of the RT code.  That seems like the best way to separate the system without losing too much resources.
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