Shrinking the IBM Roadrunner Supercomputer to desktop formfactor - Wafer Scale Integration
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From: Andrew Reilly on 19 Jun 2008 19:35 On Thu, 19 Jun 2008 13:43:30 +0000, Stephen Fuld wrote: > perhaps to reduce the size of the internal blocks so that, in > combination with the longer transfers, you eliminate the Columns and the > associated latency. I.e. you just give the DRAM a row address and it > blasts the whole row into the CPU chip as very high speed. I've seen that done, but on-chip. Ten years ago I came across the Mitsubishi M32R/D, which was a 32-bit RISC with (guess? 2M) on-chip DRAM. The bus between the processor cache and the DRAM was a whole row wide, and it read rows at once. Not sure whether it had to write whole rows at once, but maybe. I think it was intended for digital cameras. Cheers, -- Andrew |