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From: analog_fever on 29 Jun 2010 12:03
I am designing filter to do decimation at the output of a Sigma Delta
modulator. Here is the spec -

Sampling frequency - Fs - 1.4MHz
Decimation factor - D - 100
Input - 3 bits
Output resolution - 13 bits.

The filter, and the modulator are reset every 100 clock cycles.

I tried using a CIC filter, but since it is to be reset every 100 clock
cycles, I am limited to order 1. I will not get 13 bit resolution with 1
order.

I am looking at two stage filter now. The questions are

1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
Second stage - Order 4 with decimation 5, or something similar

2. Any pointers to two stage decimation filter design are appreciated.

The important point is that the filter is to be reset every 100 clock
cycles.


From: Tim Wescott on 29 Jun 2010 12:12
On 06/29/2010 09:03 AM, analog_fever wrote:
> I am designing filter to do decimation at the output of a Sigma Delta
> modulator. Here is the spec -
>
> Sampling frequency - Fs - 1.4MHz
> Decimation factor - D - 100
> Input - 3 bits
> Output resolution - 13 bits.
>
> The filter, and the modulator are reset every 100 clock cycles.
>
> I tried using a CIC filter, but since it is to be reset every 100 clock
> cycles, I am limited to order 1. I will not get 13 bit resolution with 1
> order.
>
> I am looking at two stage filter now. The questions are
>
> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
> Second stage - Order 4 with decimation 5, or something similar
>
> 2. Any pointers to two stage decimation filter design are appreciated.
>
> The important point is that the filter is to be reset every 100 clock
> cycles.
>
>
Why must it be reset after 100 clock cycles?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
From: analog_fever on 29 Jun 2010 12:38
>On 06/29/2010 09:03 AM, analog_fever wrote:
>> I am designing filter to do decimation at the output of a Sigma Delta
>> modulator. Here is the spec -
>>
>> Sampling frequency - Fs - 1.4MHz
>> Decimation factor - D - 100
>> Input - 3 bits
>> Output resolution - 13 bits.
>>
>> The filter, and the modulator are reset every 100 clock cycles.
>>
>> I tried using a CIC filter, but since it is to be reset every 100 clock
>> cycles, I am limited to order 1. I will not get 13 bit resolution with
1
>> order.
>>
>> I am looking at two stage filter now. The questions are
>>
>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
>> Second stage - Order 4 with decimation 5, or something similar
>>
>> 2. Any pointers to two stage decimation filter design are appreciated.
>>
>> The important point is that the filter is to be reset every 100 clock
>> cycles.
>>
>>
>Why must it be reset after 100 clock cycles?
>
>--
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>

That is a requirement from the modulator design. It, and the filter is to
be reset at the start of each ADC conversion.
From: Jerry Avins on 29 Jun 2010 12:49
On 6/29/2010 12:38 PM, analog_fever wrote:
>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>> I am designing filter to do decimation at the output of a Sigma Delta
>>> modulator. Here is the spec -
>>>
>>> Sampling frequency - Fs - 1.4MHz
>>> Decimation factor - D - 100
>>> Input - 3 bits
>>> Output resolution - 13 bits.
>>>
>>> The filter, and the modulator are reset every 100 clock cycles.
>>>
>>> I tried using a CIC filter, but since it is to be reset every 100 clock
>>> cycles, I am limited to order 1. I will not get 13 bit resolution with
> 1
>>> order.
>>>
>>> I am looking at two stage filter now. The questions are
>>>
>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation 20,
>>> Second stage - Order 4 with decimation 5, or something similar
>>>
>>> 2. Any pointers to two stage decimation filter design are appreciated.
>>>
>>> The important point is that the filter is to be reset every 100 clock
>>> cycles.
>>>
>>>
>> Why must it be reset after 100 clock cycles?
>>
>> --
>>
>> Tim Wescott
>> Wescott Design Services
>> http://www.wescottdesign.com
>>
>> Do you need to implement control loops in software?
>> "Applied Control Theory for Embedded Systems" was written for you.
>> See details at http://www.wescottdesign.com/actfes/actfes.html
>>
>
> That is a requirement from the modulator design. It, and the filter is to
> be reset at the start of each ADC conversion.

Filters have startup transients. How are repeated transients handled?

Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������
From: analog_fever on 29 Jun 2010 13:32
>On 6/29/2010 12:38 PM, analog_fever wrote:
>>> On 06/29/2010 09:03 AM, analog_fever wrote:
>>>> I am designing filter to do decimation at the output of a Sigma
Delta
>>>> modulator. Here is the spec -
>>>>
>>>> Sampling frequency - Fs - 1.4MHz
>>>> Decimation factor - D - 100
>>>> Input - 3 bits
>>>> Output resolution - 13 bits.
>>>>
>>>> The filter, and the modulator are reset every 100 clock cycles.
>>>>
>>>> I tried using a CIC filter, but since it is to be reset every 100
clock
>>>> cycles, I am limited to order 1. I will not get 13 bit resolution
with
>> 1
>>>> order.
>>>>
>>>> I am looking at two stage filter now. The questions are
>>>>
>>>> 1. Will a 2 stage CIC work? First stage - Order 5, with decimation
20,
>>>> Second stage - Order 4 with decimation 5, or something similar
>>>>
>>>> 2. Any pointers to two stage decimation filter design are
appreciated.
>>>>
>>>> The important point is that the filter is to be reset every 100 clock
>>>> cycles.
>>>>
>>>>
>>> Why must it be reset after 100 clock cycles?
>>>
>>> --
>>>
>>> Tim Wescott
>>> Wescott Design Services
>>> http://www.wescottdesign.com
>>>
>>> Do you need to implement control loops in software?
>>> "Applied Control Theory for Embedded Systems" was written for you.
>>> See details at http://www.wescottdesign.com/actfes/actfes.html
>>>
>>
>> That is a requirement from the modulator design. It, and the filter is
to
>> be reset at the start of each ADC conversion.
>
>Filters have startup transients. How are repeated transients handled?
>
>Jerry
>--
>Engineering is the art of making what you want from things you can get.
>�����������������������������������������������������������������������
>

Have not really thought about what you mentioned.
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