Signed addition
in [FPGA]
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From: news.green.ch on 7 Sep 2005 00:21 Hi I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how to define a signed number? I've the following situation: reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 reg [7..0] p2 // is the unsigned value that we should have 0..255 now I want to substract p1-p2, to have the differenz, to correct the error reg[7..0] diff //should be a signed value how do I define this in Verilog HDL best regards remo ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups ----= East and West-Coast Server Farms - Total Privacy via Encryption =----
From: Sylvain Munaut on 7 Sep 2005 06:11 news.green.ch wrote: > Hi > I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how > to define a signed number? > I've the following situation: > > reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 > reg [7..0] p2 // is the unsigned value that we should have 0..255 > > now I want to substract p1-p2, to have the differenz, to correct the error > reg[7..0] diff //should be a signed value > > how do I define this in Verilog HDL > > > best regards remo > > > > ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups > ----= East and West-Coast Server Farms - Total Privacy via Encryption =---- Signed and unsigned addition are the same. Their results is to be interpreted differently though ... Let's says the number are 4 bits unsigned : 1001 = 9 0100 = 4 -------- 01101 = 13 now if they are 4 signed : 1001 = -7 0100 = 4 --------- 01101 = -3 See, the method to do the computation is the same but what it _means_ is different ... Now, you want to substract 2 unsigned number of seven bits so the result to avoid overflow should be 9 bits. I don't know verilog but in vhdl that would give diff <= ('0' & p1) - ('0' & p2); The synthesis tool should be smart enough to figure out to use a 8 bit adder, input 1 to the start of the carry chain, inverting p2 and outputing the carry to the 9th bit of diff. Sylvain
From: Simon Peacock on 7 Sep 2005 06:15 almost right 01101 /= -3 11101 = -3 you need to sign extend ;-) Simon "Sylvain Munaut" <com.246tNt(a)tnt> wrote in message news:431ebc5a$0$27788$ba620e4c(a)news.skynet.be... > news.green.ch wrote: > > Hi > > I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how > > to define a signed number? > > I've the following situation: > > > > reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 > > reg [7..0] p2 // is the unsigned value that we should have 0..255 > > > > now I want to substract p1-p2, to have the differenz, to correct the error > > reg[7..0] diff //should be a signed value > > > > how do I define this in Verilog HDL > > > > > > best regards remo > > > > > > > > ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- > > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups > > ----= East and West-Coast Server Farms - Total Privacy via Encryption =---- > > Signed and unsigned addition are the same. Their results is to be > interpreted differently though ... > > Let's says the number are 4 bits unsigned : > > 1001 = 9 > 0100 = 4 > -------- > 01101 = 13 > > now if they are 4 signed : > 1001 = -7 > 0100 = 4 > --------- > 01101 = -3 > > > See, the method to do the computation is the same but what it _means_ is > different ... > > > Now, you want to substract 2 unsigned number of seven bits so the result > to avoid overflow should be 9 bits. I don't know verilog but in vhdl > that would give > > diff <= ('0' & p1) - ('0' & p2); > > The synthesis tool should be smart enough to figure out to use a 8 bit > adder, input 1 to the start of the carry chain, inverting p2 and > outputing the carry to the 9th bit of diff. > > > Sylvain
From: Sylvain Munaut on 7 Sep 2005 07:17 Simon Peacock wrote: > almost right > 01101 /= -3 > 11101 = -3 > > you need to sign extend ;-) Damn, my bad ... typed quicker than I thought ;) > > Simon > > "Sylvain Munaut" <com.246tNt(a)tnt> wrote in message > news:431ebc5a$0$27788$ba620e4c(a)news.skynet.be... > >>news.green.ch wrote: >> >>>Hi >>>I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but > > how > >>>to define a signed number? >>>I've the following situation: >>> >>>reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 >>>reg [7..0] p2 // is the unsigned value that we should have 0..255 >>> >>>now I want to substract p1-p2, to have the differenz, to correct the > > error > >>>reg[7..0] diff //should be a signed value >>> >>>how do I define this in Verilog HDL >>> >>> >>>best regards remo >>> >>> >>> >>>----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet > > News==---- > >>>http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ > > Newsgroups > >>>----= East and West-Coast Server Farms - Total Privacy via Encryption > > =---- > >>Signed and unsigned addition are the same. Their results is to be >>interpreted differently though ... >> >>Let's says the number are 4 bits unsigned : >> >> 1001 = 9 >> 0100 = 4 >> -------- >>01101 = 13 >> >>now if they are 4 signed : >> 1001 = -7 >> 0100 = 4 >>--------- >>01101 = -3 >> >> >>See, the method to do the computation is the same but what it _means_ is >>different ... >> >> >>Now, you want to substract 2 unsigned number of seven bits so the result >>to avoid overflow should be 9 bits. I don't know verilog but in vhdl >>that would give >> >>diff <= ('0' & p1) - ('0' & p2); >> >>The synthesis tool should be smart enough to figure out to use a 8 bit >>adder, input 1 to the start of the carry chain, inverting p2 and >>outputing the carry to the 9th bit of diff. >> >> >>Sylvain > > >
From: Paulo Dutra on 7 Sep 2005 18:58 wire signed [9:0] op1; assign op1 = subtract_u11[9:0]; assign add_u3 = 12'sh7E1 + multiply_u3_b_signed; 0x7E1 is a signed constant by definition of the 's news.green.ch wrote: > Hi > I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how > to define a signed number? > I've the following situation: > > reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 > reg [7..0] p2 // is the unsigned value that we should have 0..255 > > now I want to substract p1-p2, to have the differenz, to correct the error > reg[7..0] diff //should be a signed value > > how do I define this in Verilog HDL > > > best regards remo > > > > ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==---- > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups > ----= East and West-Coast Server Farms - Total Privacy via Encryption =---- -- / 7\'7 Paulo Dutra (paulo.dutra(a)xilinx.com) \ \ ` Xilinx hotline(a)xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USA
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