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From: Michael on 15 Apr 2008 13:44
On Apr 15, 12:43 pm, "HT-Lab" <han...(a)ht-lab.com> wrote:
> "Kevin Neilson" <kevin_neil...(a)removethiscomcast.net> wrote in message
>
> news:fu2ku0$aep3(a)cnn.xsj.xilinx.com...
>
>
>
>
>
> > Michael wrote:
> >> Howdy - I'm just getting started with FPGAs. In college I remember we
> >> used ModelSim with ISE for FPGA simulation. We were able to get a
> >> license through our school for free. Like a fool I no longer have that
> >> license, so what free options are out there? I saw that there is
> >> something called ModelSim Xilinx Edition III Starter (http://
> >>www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
> >> limited feature package, or a time limited package. Is that what I
> >> want? Or is there something else I should be looking at?
>
> >> Thanks!
>
> >> -Michael
>
> > The ModelSim starter is limited.  I think the main limitation is that it
> > is programmed to get radically slower as the number of lines of HDL
> > increases.  -Kevin
>
> Starter edition slows down to 1% of PE (basically grinds to a halt) after
> 10000 lines (executable lines), below 10000 lines it operates at 30% of PE..
>
> MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.
>
> There is no swift, mixed language or SystemC support in either version.
>
> Hanswww.ht-lab.com

Hi Hans - thanks for the information. I'm not terribly worried about
speed at the moment - I'm just trying to learn the basics for now. Do
you know how the student edition (http://www.model.com/resources/
student_edition/student_default.asp) compares to these? It can't
handle mixed HDL designs which seems a bit of a handicap - but I can
work around that. I couldn't find any mention of a limit on speed or
the number of executable lines.

Also - is there a Xilinx simulator that is built into ISE? I am
following a Xilinx tutorial (http://www.xilinx.com/support/techsup/
tutorials/tutorials9.htm) and it first says "Whether you use
the ModelSim simulator or the ISE Simulator with this tutorial, you
will achieve the same results." suggesting there is a fully functional
tutorial built into ISE, and then two paragraphs down it says "In
order to use this tutorial, you must install ModelSim on your
computer.". So that just confused me.

Thanks!

-Michael
From: Kevin Neilson on 15 Apr 2008 14:10

> Also - is there a Xilinx simulator that is built into ISE? I am
> following a Xilinx tutorial (http://www.xilinx.com/support/techsup/
> tutorials/tutorials9.htm) and it first says "Whether you use
> the ModelSim simulator or the ISE Simulator with this tutorial, you
> will achieve the same results." suggesting there is a fully functional
> tutorial built into ISE, and then two paragraphs down it says "In
> order to use this tutorial, you must install ModelSim on your
> computer.". So that just confused me.
>
> Thanks!
>
> -Michael
The most recent version of ISIM (the ISE simulator) is much faster and
has a new parser so it supports the language(s) much better. The user
interface is a bit coarser and the waveform viewer is not as nice as
Modelsim's, but it might work well for you. I didn't consider this
because it's not really free, since ISE isn't free, but if you already
have ISE it might be a good option. -Kevin
From: Michael on 15 Apr 2008 14:34
On Apr 15, 2:10 pm, Kevin Neilson
<kevin_neil...(a)removethiscomcast.net> wrote:
> > Also - is there a Xilinx simulator that is built into ISE? I am
> > following a Xilinx tutorial (http://www.xilinx.com/support/techsup/
> > tutorials/tutorials9.htm) and it first says "Whether you use
> > the ModelSim simulator or the ISE Simulator with this tutorial, you
> > will achieve the same results." suggesting there is a fully functional
> > tutorial built into ISE, and then two paragraphs down it says "In
> > order to use this tutorial, you must install ModelSim on your
> > computer.". So that just confused me.
>
> > Thanks!
>
> > -Michael
>
> The most recent version of ISIM (the ISE simulator) is much faster and
> has a new parser so it supports the language(s) much better.  The user
> interface is a bit coarser and the waveform viewer is not as nice as
> Modelsim's, but it might work well for you.  I didn't consider this
> because it's not really free, since ISE isn't free, but if you already
> have ISE it might be a good option.  -Kevin

I'm confused - I just downloaded the "ISE WebPACK 9.2i" a couple days
ago and didn't pay a thing. (and it never asked me to pay a thing).
Does this have a built in simulator, or is it only the version that
you pay for that has a built in simulator? Thanks,

-Michael
From: HT-Lab on 15 Apr 2008 15:42

"Michael" <nleahcim(a)gmail.com> wrote in message
news:d46de822-ec69-411f-9c02-1d98727b9f46(a)d26g2000prg.googlegroups.com...
On Apr 15, 12:43 pm, "HT-Lab" <han...(a)ht-lab.com> wrote:
> "Kevin Neilson" <kevin_neil...(a)removethiscomcast.net> wrote in message
>
> news:fu2ku0$aep3(a)cnn.xsj.xilinx.com...
>
>
>
>
>
> > Michael wrote:
> >> Howdy - I'm just getting started with FPGAs. In college I remember we
> >> used ModelSim with ISE for FPGA simulation. We were able to get a
> >> license through our school for free. Like a fool I no longer have that
> >> license, so what free options are out there? I saw that there is
> >> something called ModelSim Xilinx Edition III Starter (http://
> >>www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
> >> limited feature package, or a time limited package. Is that what I
> >> want? Or is there something else I should be looking at?
>
> >> Thanks!
>
> >> -Michael
>
> > The ModelSim starter is limited. I think the main limitation is that it
> > is programmed to get radically slower as the number of lines of HDL
> > increases. -Kevin
>
> Starter edition slows down to 1% of PE (basically grinds to a halt) after
> 10000 lines (executable lines), below 10000 lines it operates at 30% of
> PE.
>
> MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.
>
> There is no swift, mixed language or SystemC support in either version.
>
> Hanswww.ht-lab.com

>Hi Hans - thanks for the information. I'm not terribly worried about
>speed at the moment - I'm just trying to learn the basics for now. Do
>you know how the student edition (http://www.model.com/resources/
>student_edition/student_default.asp) compares to these?

I believe it is the same speed as PE but I am not 100% sure.

>It can't handle mixed HDL designs which seems a bit of a handicap -

I agree, some companies (I don't want to mention any names
*cough*Micron*cough*) decided to only provide models in one language forcing
users to spend extra money on a dual language license, perhaps they are
sponsored by the EDA industry? :-)

Hans
www.ht-lab.com



From: lm317t on 15 Apr 2008 18:54
For behavioral sim you could go with a brand agnostic tool like ghdl
and iverilog are both free, and I've used them sucessfully for simple
to quite large designs. I find the Xilinx and Altera tools to be too
slow and cumbersome, but I haven't compared those sim tools to ghdl or
iverilog.

Basically you write your test bench in the same language as a module
that uses your hardware module, but does not have to be synthesizable
and can use all those extra language pragmas like $monitor(),
$fprintf(), $system(), etc. It is also easy to pipe the data into/out
of the testbench for external processing and verification. Waveforms
can be viewed with gtkwave.

taken from
http://www.eda.ncsu.edu/wiki/Tutorial:ASIC_Design_Tutorials#Tutorial1:_Introduction_to_Simulation_and_Synthesis
and
http://www.ece.ncsu.edu/erl/tutorials/asic.php#bs


---------------------------
test.v---------------------------------------------------------------------------------------
module test_fixture;
reg clock100 = 0 ;
reg latch = 0;
reg dec = 0;
reg [3:0] in = 4'b0101;
wire zero;
initial //following block executed only once
begin
$monitor("%b", u1.value);
$dumpfile("count.vcd"); // waveforms in this file..
//$dumpvars; // saves all waveforms
#16 latch = 1; // wait 16 ns
#10 latch = 0; // wait 10 ns
#10 dec = 1;
#100 $finish; //finished with simulation
end
always #5 clock100 = ~clock100; // 10ns clock

// instantiate modules -- call this counter u1
counter
u1( .clock(clock100), .in(in), .latch(latch), .dec(dec),
.zero(zero));
endmodule /*test_fixture*/
------------------------------------------------------------------------

--------------------
counter.v--------------------------------------------------
/*module************************************
*
* NAME: counter
*
* DESCRIPTION:
* downcounter with zero flag and synchronous clear
*
* NOTES:
*
* REVISION HISTORY
* Date Programmer Description
* 7/10/97 P. Franzon ece520-specific version
*
*M*/

/*======Declarations===============================*/

module counter (clock, in, latch, dec, zero);


/*-----------Inputs--------------------------------*/

input clock; /* clock */
input [3:0] in; /* input initial count */
input latch; /* `latch input' */
input dec; /* decrement */

/*-----------Outputs--------------------------------*/

output zero; /* zero flag */

/*----------------Nets and Registers----------------*/
/*---(See input and output for unexplained variables)---*/

reg [3:0] value; /* current count value */
wire zero;

// Count Flip-flops with input multiplexor
always@(posedge clock)
begin // begin-end not actually need here as there is only one
statement
if (latch) value <= in;
else if (dec && !zero) value <= value - 1'b1;
end

// combinational logic for zero flag
assign zero = ~|value;

endmodule /* counter */
---------------------------------


run:
iverilog counter.v test.v
../a.out

then:
gtkwave count.vcd

This is a very quick way to debug and is very similar to

On Apr 15, 3:42 pm, "HT-Lab" <han...(a)ht-lab.com> wrote:
> "Michael" <nleah...(a)gmail.com> wrote in message
>
> news:d46de822-ec69-411f-9c02-1d98727b9f46(a)d26g2000prg.googlegroups.com...
> On Apr 15, 12:43 pm, "HT-Lab" <han...(a)ht-lab.com> wrote:
>
>
>
> > "Kevin Neilson" <kevin_neil...(a)removethiscomcast.net> wrote in message
>
> >news:fu2ku0$aep3(a)cnn.xsj.xilinx.com...
>
> > > Michael wrote:
> > >> Howdy - I'm just getting started with FPGAs. In college I remember we
> > >> used ModelSim with ISE for FPGA simulation. We were able to get a
> > >> license through our school for free. Like a fool I no longer have that
> > >> license, so what free options are out there? I saw that there is
> > >> something called ModelSim Xilinx Edition III Starter (http://
> > >>www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
> > >> limited feature package, or a time limited package. Is that what I
> > >> want? Or is there something else I should be looking at?
>
> > >> Thanks!
>
> > >> -Michael
>
> > > The ModelSim starter is limited. I think the main limitation is that it
> > > is programmed to get radically slower as the number of lines of HDL
> > > increases. -Kevin
>
> > Starter edition slows down to 1% of PE (basically grinds to a halt) after
> > 10000 lines (executable lines), below 10000 lines it operates at 30% of
> > PE.
>
> > MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.
>
> > There is no swift, mixed language or SystemC support in either version.
>
> > Hanswww.ht-lab.com
> >Hi Hans - thanks for the information. I'm not terribly worried about
> >speed at the moment - I'm just trying to learn the basics for now. Do
> >you know how the student edition (http://www.model.com/resources/
> >student_edition/student_default.asp) compares to these?
>
> I believe it is the same speed as PE but I am not 100% sure.
>
> >It can't handle mixed HDL designs which seems a bit of a handicap -
>
> I agree, some companies (I don't want to mention any names
> *cough*Micron*cough*) decided to only provide models in one language forcing
> users to spend extra money on a dual language license, perhaps they are
> sponsored by the EDA industry? :-)
>
> Hanswww.ht-lab.com

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