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From: liaobojie on 1 Nov 2005 21:17
Hi,

I am trying to use a bidirectional bus, declared as inout in my vhdl
code. When running on FPGA eveything works, except that bus. The bus is
dead all the time and can not be read.

I have tried changing that port to in only, and eveything works fine.

I understand that for an inout port, tristate needs to declared. Still,
that doesn't help.

If anyone could please help out, it'd be much appreciated.

Thank you for your attention.

below is my code

--------------------------------------------------------------------------------
-- SubModule USB
-- Created 16/10/2005 6:51:41 PM
--------------------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
use ieee.std_logic_unsigned.all;

entity USB is
port (
PORTB : inout std_logic_vector(7 downto 0);
CLK : in std_logic;
RST : in std_logic;
CS : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
A : in std_logic_vector(15 downto 0);
WR : in std_logic;
RD : in std_logic;
IFCLK : in std_logic;
FIFOADR : out std_logic_vector(1 downto 0);
FLAGA : in std_logic;
FLAGB : in std_logic;
FLAGC : in std_logic;
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
PKTEND : out std_logic;
RESET : out std_logic;
WAIT_ST : out std_logic);
end USB;
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
architecture behaviour of USB is

signal SLRD_buffer : std_logic;
signal SLWR_buffer : std_logic;
signal OE :std_logic;



begin

FIFOADR( 1 downto 0) <=b"10" when ((WR = '1' and CS = '1') and A(1
downto 0) = b"11") else b"00";
SLOE<='1' when ((RD='1' and CS = '1') and A(1 downto 0) = b"01")else
'0';
SLRD<= '1' when (CS='1' and RD='1' and A(1 downto 0) = b"01") else '0';

OE<='1' when (WR='1' and CS = '1') else '0';
PORTB<=DI when (OE='1') else "ZZZZZZZZ";

DO<= x"01" when (A(1 downto 0)=b"00" and FLAGA='1' ) else
--EP2empty
x"00" when (A(1 downto 0)=b"00" and FLAGA='0' ) else --EP2 not
empty
x"01" when (A(1 downto 0)=b"10" and FLAGB='1' ) else --EP6 full
x"00" when (A(1 downto 0)=b"10" and FLAGB='0' ) else --EP6 not
full
PORTB ;
RESET<='1';
PKTEND <='0';

SLWR<='0';

end behaviour;

From: Zara on 2 Nov 2005 01:25
On 1 Nov 2005 18:17:45 -0800, liaobojie(a)gmail.com wrote:
(..)
>--------------------------------------------------------------------------------
>-- SubModule USB
>-- Created 16/10/2005 6:51:41 PM
>--------------------------------------------------------------------------------
>Library IEEE;
>Use IEEE.Std_Logic_1164.all;
>use ieee.std_logic_unsigned.all;

add these two lines:

library UNISIM;
use UNISIM.VComponents.all;

>
>entity USB is
> port (
> PORTB : inout std_logic_vector(7 downto 0);
> CLK : in std_logic;
> RST : in std_logic;
> CS : in std_logic;
> DI : in std_logic_vector(7 downto 0);
> DO : out std_logic_vector(7 downto 0);
> A : in std_logic_vector(15 downto 0);
> WR : in std_logic;
> RD : in std_logic;
> IFCLK : in std_logic;
> FIFOADR : out std_logic_vector(1 downto 0);
> FLAGA : in std_logic;
> FLAGB : in std_logic;
> FLAGC : in std_logic;
> SLOE : out std_logic;
> SLRD : out std_logic;
> SLWR : out std_logic;
> PKTEND : out std_logic;
> RESET : out std_logic;
> WAIT_ST : out std_logic);
>end USB;
>--------------------------------------------------------------------------------
>
>--------------------------------------------------------------------------------
>architecture behaviour of USB is
>
>signal SLRD_buffer : std_logic;
>signal SLWR_buffer : std_logic;
>signal OE :std_logic;
>
add this line
signal portb_in,portb_out:std_logic_vector(7 downto 0);
>
>
>begin
>
>FIFOADR( 1 downto 0) <=b"10" when ((WR = '1' and CS = '1') and A(1
>downto 0) = b"11") else b"00";
>SLOE<='1' when ((RD='1' and CS = '1') and A(1 downto 0) = b"01")else
>'0';
>SLRD<= '1' when (CS='1' and RD='1' and A(1 downto 0) = b"01") else '0';
>
>OE<='1' when (WR='1' and CS = '1') else '0';

change this line:
>PORTB<=DI when (OE='1') else "ZZZZZZZZ";
to this other:
portbio:for i in portb'range generate
portbio_bit:IOBUF(I=>portb_out(i),O=>portb_in(i),T=>OE,IO=>PORTB(i));
end generate;

>
>DO<= x"01" when (A(1 downto 0)=b"00" and FLAGA='1' ) else
>--EP2empty
> x"00" when (A(1 downto 0)=b"00" and FLAGA='0' ) else --EP2 not
>empty
> x"01" when (A(1 downto 0)=b"10" and FLAGB='1' ) else --EP6 full
> x"00" when (A(1 downto 0)=b"10" and FLAGB='0' ) else --EP6 not
>full
change this line:
> PORTB ;
to
portb_in;

>RESET<='1';
>PKTEND <='0';
>
>SLWR<='0';
>
>end behaviour;


That should do it. Sometimes you must instantiate primitives if you
want to control what you are doing.
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