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From: Wojciech Zabolotny on 9 Apr 2008 18:36
Hi All,

I need to specify the strict setup time for the group of signals.
It can be relatively high, but I need very low skew between the signals.
In Quartus for Altera FPGAs I can define it with the sdc contraints as
follows:

set_max_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 6.000
set_min_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 5.000

With the constraints above the code compiles and opperates correctly.

However in Xilinx ISE:
TIMEGRP "MY_BUS_GRP" OFFSET = IN 6 ns BEFORE "SYS_CLK"
does not allow me to specify both the minimal and maximal setup time...

As the result, I get the implementation, where for one signal the setup
time is equal to 5.99 ns, but for the other - e.g. only 3ns .
Because the signals are then oversampled at high frequency it results in
the unacceptable skew...

How can I solve this problem?
Using OFFSET IN AFTER is problematic, as I'd need to adjust all
constraints if the period of the clock changes :-(.
--
TIA & Regards,
Wojtek

From: Peter Alfke on 9 Apr 2008 19:53
On Apr 9, 3:36 pm, Wojciech Zabolotny <w...(a)ise.pw.edu.pl> wrote:
> Hi All,
>
> I need to specify the strict setup time for the group of signals.
> It can be relatively high, but I need very low skew between the signals.
> In Quartus for Altera FPGAs I can define it with the sdc contraints as
> follows:
>
> set_max_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 6.000
> set_min_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 5.000
>
> With the constraints above the code compiles and opperates correctly.
>
> However in Xilinx ISE:
> TIMEGRP "MY_BUS_GRP" OFFSET = IN 6 ns BEFORE "SYS_CLK"
> does not allow me to specify both the minimal and maximal setup time...
>
> As the result, I get the implementation, where for one signal the setup
> time is equal to 5.99 ns, but for the other - e.g. only 3ns .
> Because the signals are then oversampled at high frequency it results in
> the unacceptable skew...
>
> How can I solve this problem?
> Using OFFSET IN AFTER is problematic, as I'd need to adjust all
> constraints if the period of the clock changes :-(.
> --
> TIA & Regards,
> Wojtek

There is no way any FPGA (or other IC) can guarantee a combinatorial
plus routing delay to be 5 ns min, 6 ns max. Just normal ambient
temperature and Vcc variations exceed these tolerances, You may
perhaps be able to make the delays track (which is what you seem to be
after) but absolute delay precision is out of the question,
Now, if you register these values in a register driven by a global
clock, the Qs may have very little delta delay,
BTW, in my book, "set-up time" is a timing requirement on the D-input
of a register or flip-flop, never a physical delay. Maybe that's the
difference between the two manufacturers...
Peter Alfke, Xilinx
From: John_H on 9 Apr 2008 22:24
Wojciech Zabolotny wrote:
> Hi All,
>
> I need to specify the strict setup time for the group of signals.
> It can be relatively high, but I need very low skew between the signals.
> In Quartus for Altera FPGAs I can define it with the sdc contraints as
> follows:
>
> set_max_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 6.000
> set_min_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 5.000
>
> With the constraints above the code compiles and opperates correctly.
>
> However in Xilinx ISE:
> TIMEGRP "MY_BUS_GRP" OFFSET = IN 6 ns BEFORE "SYS_CLK"
> does not allow me to specify both the minimal and maximal setup time...
>
> As the result, I get the implementation, where for one signal the setup
> time is equal to 5.99 ns, but for the other - e.g. only 3ns .
> Because the signals are then oversampled at high frequency it results in
> the unacceptable skew...
>
> How can I solve this problem?
> Using OFFSET IN AFTER is problematic, as I'd need to adjust all
> constraints if the period of the clock changes :-(.

When signals are absolutely critical to be low skew as in oversampling
or otherwise very high speed designs, I and many others resort to using
manual placement and often constrained routes. If the routing is
regular, often one constrained route can cover a multitude of signals.

Constrained routing is an advanced feature that requires some work
inside FPGA Editor to generate the constraints. Solid knowledge of the
physical workings around the IOBs and signal routing boxes helps
significantly. Much of that knowledge comes from "poking around" inside
the chip trying different routes both automated and manual.

There are some application notes on wide, very high speed buses that use
the physical constraints to tie down how things behave coming into the
chip. How precise you get depends on how extreme your design goals are.

- John_H
From: Gabor on 10 Apr 2008 08:56
On Apr 9, 10:24 pm, John_H <newsgr...(a)johnhandwork.com> wrote:
> Wojciech Zabolotny wrote:
> > Hi All,
>
> > I need to specify the strict setup time for the group of signals.
> > It can be relatively high, but I need very low skew between the signals.
> > In Quartus for Altera FPGAs I can define it with the sdc contraints as
> > follows:
>
> > set_max_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 6.000
> > set_min_delay -from [get_ports MY_BUS[*]] -to [get_registers *] 5.000
>
> > With the constraints above the code compiles and opperates correctly.
>
> > However in Xilinx ISE:
> > TIMEGRP "MY_BUS_GRP" OFFSET = IN 6 ns BEFORE "SYS_CLK"
> > does not allow me to specify both the minimal and maximal setup time...
>
> > As the result, I get the implementation, where for one signal the setup
> > time is equal to 5.99 ns, but for the other - e.g. only 3ns .
> > Because the signals are then oversampled at high frequency it results in
> > the unacceptable skew...
>
> > How can I solve this problem?
> > Using OFFSET IN AFTER is problematic, as I'd need to adjust all
> > constraints if the period of the clock changes :-(.
>
> When signals are absolutely critical to be low skew as in oversampling
> or otherwise very high speed designs, I and many others resort to using
> manual placement and often constrained routes. If the routing is
> regular, often one constrained route can cover a multitude of signals.
>
> Constrained routing is an advanced feature that requires some work
> inside FPGA Editor to generate the constraints. Solid knowledge of the
> physical workings around the IOBs and signal routing boxes helps
> significantly. Much of that knowledge comes from "poking around" inside
> the chip trying different routes both automated and manual.
>
> There are some application notes on wide, very high speed buses that use
> the physical constraints to tie down how things behave coming into the
> chip. How precise you get depends on how extreme your design goals are.
>
> - John_H

If you can generate the required phase relationship with
your clock signal (to the sampling flip-flops) instead of
playing with the input delay to the flop D, it is fairly
simple to have a low skew sampling when you use the IOB
flip-flops. Then the only routing that comes into play is
the clock, and this can be adjusted using DCM resources.
This assumes you don't insert the delay element in each
IOB between the pin and the D. Newer Virtex parts also
have variable input delay elements that can help to remove
residual skew, but for a 1 ns window this should not be
necessary.
From: Symon on 10 Apr 2008 11:27
"John_H" <newsgroup(a)johnhandwork.com> wrote in message
news:ef-dnWJb2Lr752DanZ2dnUVZ_remnZ2d(a)comcast.com...
>
> When signals are absolutely critical to be low skew as in oversampling or
> otherwise very high speed designs, I and many others resort to using
> manual placement and often constrained routes. If the routing is regular,
> often one constrained route can cover a multitude of signals.
>
> Constrained routing is an advanced feature that requires some work inside
> FPGA Editor to generate the constraints. Solid knowledge of the physical
> workings around the IOBs and signal routing boxes helps significantly.
> Much of that knowledge comes from "poking around" inside the chip trying
> different routes both automated and manual.
>
Good advice. May I also recommend some reading for the OP?

directed routing site:xilinx.com

HTH., Syms.


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